Acromag AcroPack AP512, Руководство пользователя

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AP512 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310 - 30 - http://www.acromag.com - 30 - https://www.acromag.com
Error (FE) 1 = Framing Error - Indicates that the received
character does not have a valid stop bit (stop bit
following last data bit or parity bit detected as a
zero/space bit). This bit is reset low when the
CPU reads the contents of the LSR. In FIFO
mode, the framing error is associated with a
particular character in the FIFO (LSR Bit 3 reflects
the error when the character is at the top of the
FIFO).
4 Break
Interrupt
(BI) 0 = No Break
1 = Break the received data input has
been held in the space (logic 0) state for more
then a full-word transmission time (start bits+
data+ parity bit+ stop bits). Reset upon read of
LSR. In FIFO mode, this bit is associated with a
particular character in the FIFO and reflects the
Break Interrupt when the break character is at
the top of the FIFO. It is detected by the host
CPU during the first LSR read. Only one “0”
character is loaded into the FIFO when BI occurs.
5 Transmitter
Holding
Register
Empty
(THRE)
0 = Not Empty
1 = Empty - indicates that the channel is ready to
accept a new character for transmission. Set
high when character is transferred from the THR
into the transmitter shift register. Reset low by
loading the THR (It is not reset by a host CPU
read of the LSR). In FIFO mode, this bit is set
when the Tx FIFO is empty and cleared when one
byte is written to the Tx FIFO. When a
Transmitter Holding Register Empty interrupt is
enabled by IER bit 1, this signal causes a priority
3 interrupt in the ISR. If the ISR indicates that
this signal is causing the interrupt, the interrupt
is cleared by a read of the ISR.
6 Transmitter
Empty
(TEMT) 0 = Not Empty
1 = Transmitter Empty - set when
both the Transmitter Holding Register (THR) and
the Transmitter Shift Register (TSR) are both
empty. Reset low when a character is loaded
into the THR and remains low until the character
is transmitted (it is not reset low by a read of the
LSR). In FIFO mode, this bit is set when both the