Acromag AcroPack AP512, Руководство пользователя

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AP512 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310 - 17 - http://www.acromag.com - 17 - https://www.acromag.com
3.2 UART and Device Configuration Registers
The Device Configuration Registers and the eight individual UART
Configuration Registers occupy 8K of PCI bus memory address space. These
registers are offset from the BAR0 address as identified in the PCI
Configuration Registers in the previous section.
Each UART Configuration Register occupies 1K byte of memory space that
include the 16550 compatible registers.
The Device Configuration Registers are accessible from all UART channels,
however not all bits can be controlled by all channels. The control of the
8XMODE, 4XMODE, RESET, and SLEEP bits are only available for that
particular channel.
Table 3.2 UART and Device
Configuration Registers
Address Offset Register Function Comment
0x0000-0x000F
UART 0 Registers
See Table 3.4
0x0010-0x007F Reserved
0x0080-0x009A Device Configuration
Registers
See Table 3.3
0x009B-0x00FF Reserved Reserved
0x0100-0x01FF UART 0 FIFOs 256 bytes of FIFO data
0x0200-0x03FF UART 0 Read FIFO
with errors
256 bytes of RX FIFO data +
LSR
0x0400-0x07FF Repeat above registers for UART 1
0x0800-0x0BFF Repeat above registers for UART 2
0x0C00-0x0FFF Repeat above registers for UART 3
Table 3.3 Device Configuration Registers
Address
Offset
Register Read/Write Comments Reset State
0x0080 INT0 [7:0] Read-only Interrupt [7:0] Bits [7:0] = 0x00
0x0081 INT1[15:8] Read-only Bits [7:0] = 0x00
0x0082 INT2[23:16] Read-only Bits [7:0] = 0x00
0x0083 INT3[31:24] Read-only Bits [7:0] = 0x00
0x0084 TIMERCNTL Read/Write Timer Control Bits [7:0] = 0x00
0x0085 REGA Reserved Bits [7:0] = 0x00
0x0086 TIMERLSB Read/Write Timer LSB Bits [7:0] = 0x00
0x0087 TIMERMSB Read/WRITE Timer MSB Bits [7:0] = 0x00
Individual UART channels can only control the bit
pertaining to that channel in the registers at address
offset 0x088-0x08B