AP512 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 18 - http://www.acromag.com
- 18 -
https://www.acromag.com
0X088
8XMODE
Read/Write
Bits [7:0] = 0x00
0x089
4XMODE
Read/Write
Bits [7:0] = 0x00
0x08A
RESET
Write-only Self clear bits after executing Reset
Bits [7:0] = 0x00
0x08B
SLEEP
Read/Write Sleep mode
Bits [7:0] = 0x00
0x08C
DREV
Read-only Device revision
Bits [7:0] = Current
Rev.
0x08D
DVID
Read-only Device identification
Bits [7:0] = 0x88
0x08E
REGB
Read/Write EEPROM control
Bits [7:0] = 0x00
0x08F
MPIONT[7:0]
Read/Write MPIO[7:0] interrupt mask
Bits [7:0] = 0x00
0x090
MPIOVL[7:0]
Read/Write MPIO[7:0] level control
Bits [7:0] = 0x00
0x091
MPIO3T[7:0]
Read/Write MPIO[7:0] output control
Bits [7:0] = 0x00
0x092
MPIONC[7:0]
Read/Write MPIO[7:0] input polarity select
Bits [7:0] = 0x00
0x093
MPIOSEL[7:0]
Read/Write MPIO[7:0] select
Bits [7:0] = 0Xff
0x094
MPIOOD[7:0]
Read/Write MPIO[7:0] open-drain output control
Bits [7:0] = 0x00
0x095
MPIONT[15:8]
Read/Write MPIO[15:8] interrupt mask
Bits [15:8] = 0x00
0x096
MPIOLVL[15:8]
Read/Write MPIO[15:8] level control
Bits [15:8] = 0x00
0x097
MPIO3T[15:8]
Read/Write MPIO[15:8] output control
Bits [15:8] = 0x00
0X098
MPIOINV[15:8]
Read/Write MPIO[15:8] input polarity select
Bits [15:8] = 0x00
0x099
MPIOSEL[15:8]
Read/Write MPIO[15:8] select
Bits [15:8] = 0xFF
0x09A
MPIOOD[15:8]
Read/Write MPIO[15:8] open-drain output control
Bits [15:8] = 0x00
0x09B
Reserved
0x00
3.2.1 UART Channel Configuration Registers
There are two methods to load transmit data and unload receive data from
each UART channel. First, there is a transmit data register and receive data
register for each UART channel as shown in Table 3.2 set to ease
programming. These registers support 8, 16
,
24 and 32 bits wide format. In
the 32-bit format, it increases the data transfer rate on the PCI bus.
Additionally, a special register location provides receive data byte with its
associated error flags. This is a 16-bit or 32-bit read operation where the
Line Status Register (LSR) content in the UART channel register is paired
along with the data byte. This operation further facilitates data unloading
with the error flags without having to read the LSR register separately.
Furthermore, the XR17V358 supports 32-bit read/write operation.
The second method is through each UART channel’s transmit holding
register (THR) and receive holding register (RHR). The THR and RHR registers
are 16550 compatible so their access is limited to 8-bit format. The software
driver must separately read the LSR content for the associated error flags
before reading the data byte.
FIFO Data Loading and Unloading n 32-bit Format
The XR17V358 supports 32-bit Read and 32-bit Write transactions anywhere
in the mapped memory region (except reserved areas). In addition, to utilize
this feature fully, the device provides a separate memory location (apart
from the individual channel’s register set) where the RX and the TX FIFO can
be read from/written to, as shown in Table 3.2. The following is an extract
from the table showing the memory locations that support 32-bit
