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SERIES AP441 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 29 -
http://www.acromag.com
- 29 -
www.acromag.com
memory read/write. In addition, the PCIe target interface uses a single 4K
base address register, and implements target abort, retry, and disconnect.
The AP441 logic also implements interrupt requests via the PCIe bus.
A FPGA device provides the control signals required to operate the board. It
decodes the selected addresses, control signals, and interrupt handling. It
also returns the acknowledgement messages required by the carrier/CPU
board per the PCIe specification. The program for the FGPA is stored in
separate Flash memory and loaded upon power-up.