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SERIES AP441 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 23 -
http://www.acromag.com
- 23 -
www.acromag.com
Table 3.5 Debounce Duration
Register Channels 0 to 15
(Channels 16 to 31 and 32 to
47 similar)
Bit(s)
FUNCTION
1 to 0
Channel 0 Debounce Value
00
3-4us
01
48-64us
10
0.75-1ms
11
6-8ms
3 to 2
Channel 1 Debounce Value
00
3-4us
01
48-64us
10
0.75-1ms
11
6-8ms
.
.
.
Channel x Debounce Value
00
3-4us
01
48-64us
10
0.75-1ms
11
6-8ms
15 to
14
Channel 7 Debounce Value
00
3-4us
01
48-64us
10
0.75-1ms
11
6-8ms
Software Reset Register (Write Only)
(BAR0 + 0x0000 0078)
Writing a 1 to the bit 0 position of this register will cause a software reset to
occur. This bit is not stored and merely acts as a trigger for software reset
generation (this bit will always read back as 0). The Interrupt Enable Bit of
the Interrupt Enable and Status register is not cleared in response to a
software reset. Bits 1-7 of this register are not used and will always read as
zero.
XADC Status/Control Register (Read/Write)
(BAR0 + 0x0000 007C)
This read/write register will access the XADC register at the address set in
the XADC Address Register. This allows the board’s temperature and supply
voltages to be read.
For example, the address of the XADC Status register that is to be accessed
is first set via the XADC Address register at BAR0 plus 0x74H. Next, this
register at BAR0 plus 0x70H is read. Bits 22 to 16 of this register hold the
address of the XADC register that is accessed. Data bits 15 to 6 of this
register hold the “ADCcode” temperature, Vccint, or Vccaux value. Data bits
5 to 0 are not used. Valid addresses are given in column one of the table
below.
Reading or writing this register is possible via 32-bit data transfers.
The 10-bits digitized and output from the ADC can be converted to
temperature by using the following equation.