SERIES AP441 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 26 -
http://www.acromag.com
- 26 -
www.acromag.com
With debounce, an incoming signal must be stable for the entire debounce
time before it is recognized by the I/O or event sense logic. Debounce is
applied to both inputs and event sense inputs.
A debounce value of 4us, 64us, 1ms, or 8ms may be selected (see the
Debounce Duration Registers). As such, an incoming signal transition must
be stable for the debounce time before it is recognized by the I/O pin or
event sense logic.
Upon initialization of the debounce circuitry, be sure to delay at least the
programmed debounce time before reading any of the input channels or
event signals to ensure that the input data is valid prior to being used by the
software.
Interrupt Generation
This model provides control for generation of interrupts on change-of-state,
or positive or negative events, for all 32 channels. Interrupts are only
generated when events are enabled via the Event Enable registers. Writing
“1” to the corresponding event sense bit in the Event Pending/Clear register
will clear the event. Interrupts may be reflected internally and reported by
polling the module. Control of this feature is done via bit 0 of the Interrupt
Enable Register.
The event sense status is a flag that is raised when a specific change-of-state,
positive, or negative transition has occurred for a given I/O point, while the
state refers to its current level. Enabling both an Event Sense bit and the
board interrupts will allow interrupts to be generated
Note that the Interrupt Enable Register is cleared following a power-up or
bus initiated hardware reset, but not a software reset initiated via writing a
one to bit 0 of the Software Reset Register. Keep this in mind when you wish
to preserve the information in these two registers following a reset.
Programming Example
The following example outlines the steps necessary to configure the AP441
to setup event-generated interrupts, configure debounce, and read inputs. It
is assumed that the module has been reset and no prior (non-default)
configuration exists.
For this example, we will configure Port A inputs as an 4-channel change-of-
state detector. Any change-of-state detected on these input signal lines will
cause an interrupt to be generated.
1.
The default debounce duration is 4µs. This time applies to the FPGA
input signal and does not include opto-coupler delay. Write 0x0055
to the Debounce Duration Register at BAR0 + 0x0000 0068 to select
a 64µs debounce time for channels 0 thru 3. An incoming signal must
be stable for the entire debounce time before it will be recognized as
a valid input transition.
