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SERIES AP441 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 17 -
http://www.acromag.com
- 17 -
www.acromag.com
CONFIGURATION REGISTERS
The PCIe specification requires software driven initialization and
configuration via the Configuration Address space. This board provides 512
bytes of configuration registers for this purpose. It contains the
configuration registers shown in the following table to facilitate Plug-and-
Play compatibility.
The Configuration Registers are accessed via the Configuration Address and
Data Ports. The most important Configuration Registers are the Base
Address Registers which must be read to determine the base address
assigned to the board and the Interrupt Register which must be read to
determine the interrupt request that goes active on a board interrupt
request.
Table 3.1 Configuration
Registers
Reg.
Num.
D31 D24
D23 D16
D15 D8
D7 D0
0
Device ID
0x7031 AP441-1E-LF
0x7032 AP441-2E-LF
0x7033 AP441-3E-LF
Vendor ID
16D5
1
Status
Command
2
Class Code=118000
Rev ID=00
3
BIST
Header
Latency
Cache
4
64-bit Memory Base Address for Memory Accesses to PCIe
interrupt and I/O registers
4K Space (BAR0)
5:10
Not Used
11
Subsystem ID
0x7031 AP441-1E-LF
0x7032 AP441-2E-LF
0x7033 AP441-3E-LF
Subsystem Vendor ID
16D5
12
Not Used
13,14
Reserved
15
Max_Lat
Min_Gnt
Inter. Pin
Inter. Line
This board is allocated a 4K byte block of memory (BAR0), to access the PCIe
interrupt and I/O registers. The PCIe bus decodes 4K bytes for BAR0 for this
memory space.
This board is addressable in the PCIe memory space to control the
configuration and status monitoring of 32 digital input or event channels.