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SERIES AP441 ACROPACK
USER
’S MANUAL
Acromag, Inc. Tel: 248-295-0310
- 19 -
http://www.acromag.com
- 19 -
www.acromag.com
Interrupt Enable Status Register (Read/Write)
(BAR0 + 0x0000 0000)
This read/write register is used to: enable board interrupts and determine
the pending status of interrupts.
The function of each of the interrupt register bits are described in Table 3.3.
This register can be read or written with either 8-bit, 16-bit, or 32-bit data
transfers. A power-up or system reset sets all interrupt register bits to 0.
With both an enabled Event Sense bit and Board Interrupt Enable bit, then
interrupts can be generated.
Table 3.3 Interrupt Register
Note that any registers/bits not
mentioned will remain at the
default value logic low.
Bit(s)
FUNCTION
0
Board Interrupt Enable Bit. This bit must be set to logic “1” to
enable generation of interrupts from the AP module. Setting
this bit to logic “0” will disable board interrupts. (Read/Write
Bit)
0
Disabled
1
Enabled
1
Board Interrupt Pending Status Bit. This bit can be read to
determine the interrupt pending status of the AP module.
When this bit is logic “1” an interrupt is pending and will cause
an interrupt request if bit-0 of the register is set. When this bit
is logic “0” and interrupt is not being requested.
0
No Interrupt
1
Interrupt Pending
0x0054
7:0
Event Pending/Clear Register IN24-IN31
0x0058
7:0
Debounce Control Register IN00-IN07
0x005C
7:0
Debounce Control Register IN08-IN15
0x0060
7:0
Debounce Control Register IN16-IN23
0x0064
7:0
Debounce Control Register IN24-IN31
0x0068
15:0
Debounce Duration Register IN00-IN07
0x006C
15:0
Debounce Duration Register IN08-IN15
0x0070
15:0
Debounce Duration Register IN16-IN23
0x0074
15:0
Debounce Duration Register IN24-IN31
0x0078
0
Software Reset Register
0x007C
32:0
XADC Status/Control Register
0x0080
32:0
XADC Address Register
0x0084→0x01FC
-
Not Used
0x0200
7:0
Firmware Revision Register