INDUSTRIAL I/O PACK SERIES ACPC8625 CompactPCI BUS CARRIER BOARD
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3. This access time assumes zero IP module wait states. For each
IP module wait state 250n seconds must be added to this value.
FIELD GROUNDING CONSIDERATIONS
Carrier boards are designed with passive filters on each supply
line to each IP module. This provides maximum filtering and signal
decoupling between the IP modules and the carrier board. However,
the boards are considered non-isolated, since there is electrical
continuity between the CompactPCI bus and the IP grounds.
Therefore, unless isolation is provided on the IP module itself, the
field I/O connections are not isolated from the CompactPCI bus.
Care should be taken in designing installations without isolation to
avoid ground loops and noise pickup. This is particularly important
for analog I/O applications when a high level of accuracy/resolution
is needed (12-bits or more). Contact your Acromag representative
for information on our many isolated signal conditioning products
that could be used to interface to the IP input/output modules.
3.0 PROGRAMMING INFORMATION
This Section provides the specific information necessary to
program and operate the ACPC8625 non-intelligent carrier board.
This Acromag ACPC8625 complies with PCI Specification
Version 2.1 and CompactPCI Specification PICMG 2.0 R2.1. It is a
CompactPCI bus slave carrier board for Industrial I/O Pack
mezzanine (IP) modules. The carrier connects a CompactPCI host
bus to the IP module’s 16-bit data bus per the Industrial I/O Pack
logic interface specification on the mezzanine (IP) modules which
are installed on the carrier.
The CompactPCI bus is defined to address three distinct
address spaces: I/O, memory, and configuration space. The IP
modules can be accessed via the CompactPCI bus memory
space only.
The CompactPCI card’s configuration registers are initialized by
system software at power-up to configure the card. The
CompactPCI carrier is a Plug-and-Play card. As a Plug-and-Play
card the board’s base address and system interrupt request line are
not selected via jumpers but are assigned by system software upon
power-up via the configuration registers. A CompactPCI bus
configuration access is used to access a CompactPCI card’s
configuration registers.
CompactPCI Configuration Address Space
When the computer is first powered-up, the computer’s system
configuration software scans the CompactPCI bus to determine
what CompactPCI devices are present. The software also
determines the configuration requirements of the CompactPCI card.
The system software accesses the configuration registers to
determine how many blocks of memory space the carrier requires. It
then programs the carrier’s configuration registers with the unique
memory address range assigned.
The configuration registers are also used to indicate that the
CompactPCI carrier requires an interrupt request line. The system
software then programs the configuration registers with the interrupt
request line assigned to the CompactPCI carrier.
Since this CompactPCI carrier is relocatable and not hardwired
in address space, this carrier’s mapping and IRQ information is
stored in the carrier’s Configuration Space registers.
Configuration Transactions
The CompactPCI bus is designed to recognize certain I/O
accesses initiated by the host processor as a configuration access.
Configuration uses two 32-bit I/O ports located at addresses 0CF8
and 0CFC hex. These two ports are:
•
32-bit configuration address port, occupying I/O addresses
0CF8 through 0CFB hex.
•
32-bit configuration data port, occupying I/O addresses 0CFC
through 0CFF hex.
Configuration space is accessed by writing a 32-bit long-word
into the configuration address port that specifies the CompactPCI
bus, the carrier board on the bus, and the configuration register on
the carrier being accessed. A read or write to the configuration data
port will then cause the configuration address value to be translated
to the requested configuration cycle on the CompactPCI bus.
Accesses to the configuration data port determine the size of the
access to the configuration register addressed and can be an 8, 16,
or 32-bit operation.
Any access to the Configuration address port that is not a 32-bit
access is treated like a normal computer I/O access. Thus,
computer I/O devices using 8 or 16-bit registers are not affected
because they will be accessed as expected.
Table 3.1: Configuration Address Port
BIT
FUNCTION
31
Enables accesses to Configuration Data to be
translated to configuration cycles on the CompactPCI
bus.
30-24
Reserved, Return 0 when read.
23-16
Bus Number
Choose a specific CompactPCI bus in the
system.
15-11
Device Number
Choose a specific device/CompactPCI board on
the bus.
10-8
Function Number
Choose a specific function in a device. Function
number is zero for the ACPC8625.
7-2
Register Number
Used to indicate which CompactPCI
Configuration Register to access. The
Configuration Registers and their corresponding
register numbers are given in Table 3.2.
1-0
Read Only bits that return 0.
Configuration Registers
The CompactPCI specification requires software driven
initialization and configuration via the Configuration Address space.
This CompactPCI carrier provides 256 bytes of configuration
registers for this purpose as shown in Table 3.2, to facilitate Plug-
and-Play compatibility.
The Configuration Registers are accessed via the Configuration
Address and Data Ports. The most important Configuration
Registers are the Base Address Registers and the Interrupt Line
Register which must be read to determine the base address
assigned to the carrier and the interrupt request line that goes active
on a carrier interrupt request.
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