INDUSTRIAL I/O PACK SERIES ACPC8625 CompactPCI BUS CARRIER BOARD
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P1, P3, P5, and P7 are 50-pin male plug header connectors.
These AMP 173280-3 connectors mate to AMP 173279-3
connectors (or similar) on the IP modules. This provides excellent
connection integrity and utilizes gold plating in the mating area.
Threaded metric M2 screws and spacers (supplied with Acromag IP
modules) provide additional stability for harsh environments (see
Drawing 4501-788 & 789 for assembly details).
Pin assignments for these connectors are made by the specific
IP model used and correspond identically to the pin numbers of the
transition module panel connectors.
IP Logic Interface Connectors (IP modules A through D)
The logic interface sides of IP modules A through D mate to
connectors P2, P4, P6, and P8 respectively, on the carrier board. IP
location is silk-screened on the board for easy identification. Field
and logic side connectors are keyed to avoid incorrect assembly.
P2, P4, P6, and P8 are 50-pin male plug header connectors.
These AMP 173280-3 connectors mate to AMP 173279-3
connectors (or similar) on the IP modules. This provides excellent
connection integrity and utilizes gold plating in the mating area.
Threaded metric M2 screws and spacers (supplied with Acromag IP
modules) provide additional stability for harsh environments (see
Drawing 4501-789 for assembly details).
Pin assignments for these connectors are defined by the IP
module specification and are shown in Table 2.1:
Table 2.1: Standard IP Logic Interface Connections (P2,4,6,8)
Pin Description
Number
Pin Description
Number
GND
1
GND
26
CLK
2
+5V
27
Reset*
3
R/W*
28
D00
4
IDSEL*
29
D01
5
DMAReq0*
30
D02
6
MEMSEL*
31
D03
7
DMAReq1*
32
D04
8
IntSel*
33
D05
9
DMAck0*
34
D06
10
IOSEL*
35
D07
11
RESERVED
36
D08
12
A1
37
D09
13
DMAEnd*
38
D10
14
A2
39
D11
15
ERROR*
40
D12
16
A3
41
D13
17
INTReq0*
42
D14
18
A4
43
D15
19
INTReq1*
44
BS0*
20
A5
45
BS1*
21
STROBE*
46
-12V
22
A6
47
+12V
23
ACK*
48
+5V
24
RESERVED
49
GND
25
GND
50
Asterisk (*) is used to indicate an active-low signal.
BOLD ITALIC Logic Lines are NOT USED by the carrier board.
CompactPCI Bus Connections for J1
Table 2.2 indicates the pin assignments for the CompactPCI
bus signals at the J1 connector. The J1 connector is the lower rear
connector on the ACPC8625 board, as viewed from the front. The
connector consists of 25 rows of six pins labeled A, B, C, D, E and
F. Pin A1 is located at the lower right hand corner of the connector
if the board is viewed from the front component side.
Refer to the CompactPCI bus specification for additional
information on the CompactPCI bus signals.
TABLE 2.2: CompactPCI bus J1 CONNECTIONS
Pin
Row A
Row B
Row C
Row D
Row E
Row F
1
+5V
-12v
TRST#
+12V
+5V
GND
2
TCK
+5V
TMS
TDO
TDI
GND
3
INTA#
INTB#
INTC#
+5V
INTD#
GND
4
BR*A4
GND
V(I/0)
INTP
INTS
GND
5
BR*A5
BR*B5
RST#
GND
GNT#
GND
6
REQ#
GND
+3.3V
CLK
AD[31]
GND
7
AD[30]
AD[29]
AD[28]
GND
AD[27]
GND
8
AD[26]
GND
V(I/O)
AD[25]
AD[24]
GND
9
C/BE[3]#
IDSEL
AD[23]
GND
AD[22]
GND
10
AD[21]
GND
+3.3V
AD[20]
AD[19]
GND
11
AD[18]
AD[17]
AD[16]
GND
C/BE[2]#
GND
12
GND
13
KEY
AREA
GND
14
GND
15
+3.3V
FRAME#
IRDY#
GND
TRDY#
GND
16
DEVSEL#
GND
V(I/O)
STOP#
LOCK#
GND
17
+3.3V
SDONE
SBO#
GND
PERR#
GND
18
SERR#
GND
+3.3V
PAR
C/BE[1]#
GND
19
+3.3V
AD[15]
AD[14]
GND
AD[13]
GND
20
AD[12]
GND
V(I/O)
AD[11]
AD[10]
GND
21
+3.3V
AD[9]
AD[8]
M66EN
C/BE[0]#
GND
22
AD[7]
GND
+3.3V
AD[6]
AD[5]
GND
23
+3.3V
AD[4]
AD[3]
+5V
AD[2]
GND
24
AD[1]
+5V
V(I/O)
AD[0]
ACK64#
GND
25
+5V
REQ64#
ENUM#
+3.3V
+5V
GND
Pound (#) is used to indicate an active-low signal.
BOLD ITALIC Logic Lines are NOT USED by the carrier board.
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