Acromag ACPC8625 Series, Руководство пользователя

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INDUSTRIAL I/O PACK SERIES ACPC8625 CompactPCI BUS CARRIER BOARD
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CompactPCI I/O Signals Connections for J4
Table 2.3 indicates the pin assignments for the CompactPCI I/O
signal mapping at the J4 connector. The J4 connector is the second
connector from the upper rear corner on the ACPC8625 board, as
viewed from the front. The connector consists of 25 rows of six pins
labeled A, B, C, D, E and F. Pin A1 is located near the center of the
board, viewed from the front component side. J4 is used to route IP
Modules A & B field signals from the carrier to the backplane.
TABLE 2.3: CompactPCI I/O Signals J4 CONNECTIONS
Pin Row A Row B Row C Row D Row E Row F
1 +3.3V +3.3V +3.3V +5V +5V GND
2 A46 A47 A48 A49 A50 GND
3 A41 A42 A43 A44 A45 GND
4 A36 A37 A38 A39 A40 GND
5 A31 A32 A33 A34 A35 GND
6 A26 A27 A28 A29 A30 GND
7 A21 A22 A23 A24 A25 GND
8 A16 A17 A18 A19 A20 GND
9 A11 A12 A13 A14 A15 GND
10 A6 A7 A8 A9 A10 GND
11 A1 A2 A3 A4 A5 GND
12 GND
13
KEY AREA
GND
14 GND
15 +3.3V +3.3V +3.3V +5V +5V GND
16 B46 B47 B48 B49 B50 GND
17 B41 B42 B43 B44 B45 GND
18 B36 B37 B38 B39 B40 GND
19 B31 B32 B33 B34 B35 GND
20 B26 B27 B28 B29 B30 GND
21 B21 B22 B23 B24 B25 GND
22 B16 B17 B18 B19 B20 GND
23 B11 B12 B13 B14 B15 GND
24 B6 B7 B8 B9 B10 GND
25 B1 B2 B3 B4 B5 GND
Note: The letter in front of the number indentifies the IP Module
Slot. The number indentifies the I/O pin number of that IP
Module.
Example: A46 A = IP Module in Slot “A”
46 = I/O Pin number “46”
(This pin on the IP Module connects to J4, Pin 2, Row A.)
BOLD ITALIC Power Lines are NOT USED by the carrier board.
The I/O signals for the J4 connector are mapped per the IP
Module I/O to CompactPCI Specification (PICMG 2.4, R1.0).
CompactPCI I/O Signals Connections for J5
Table 2.4 indicates the pin assignments for the CompactPCI I/O
signal mapping at the J5 connector. The J5 connector is the first
connector from the upper rear corner on the ACPC8625 board, as
viewed from the front. The connector consists of 22 rows of six pins
labeled A, B, C, D, E and F. Pin A22 is located at the upper left
hand corner of the connector if the board is viewed from the front
component side. J5 is used to route IP Modules C & D field signals
from the carrier to the backplane.
TABLE 2.4: CompactPCI I/O Signals J5 CONNECTIONS
Pin Row A Row B Row C Row D Row E Row F
1 +3.3V +3.3V +3.3V +5V +5V GND
2 C46 C47 C48 C49 C50 GND
3 C41 C42 C43 C44 C45 GND
4 C36 C37 C38 C39 C40 GND
5 C31 C32 C33 C34 C35 GND
6 C26 C27 C28 C29 C30 GND
7 C21 C22 C23 C24 C25 GND
8 C16 C17 C18 C19 C20 GND
9 C11 C12 C13 C14 C15 GND
10 C6 C7 C8 C9 C10 GND
11 C1 C2 C3 C4 C5 GND
12 +3.3V +3.3V +3.3V +5V +5V GND
13 D46 D47 D48 D49 D50 GND
14 D41 D42 D43 D44 D45 GND
15 D36 D37 D38 D39 D40 GND
16 D31 D32 D33 D34 D35 GND
17 D26 D27 D28 D29 D30 GND
18 D21 D22 D23 D24 D25 GND
19 D16 D17 D18 D19 D20 GND
20 D11 D12 D13 D14 D15 GND
21 D6 D7 D8 D9 D10 GND
22 D1 D2 D3 D4 D5 GND
Note: The letter in front of the number indentifies the IP Module
Slot. The number indentifies the I/O pin number of that IP
Module.
Example: C46 C = IP Module in Slot “C”
46 = I/O Pin number “46”
(This pin on the IP Module connects to J5, Pin 2, Row A.)
BOLD ITALIC Power Lines are NOT USED by the carrier board.
The I/O signals for the J5 connector are mapped per the IP
Module I/O to CompactPCI Specification (PICMG 2.4, R1.0).
DATA TRANSFER TIMING
All CompactPCI bus read or write cycles to the ACPC8625 are
typically implemented within 150n seconds (FRAME# active to
TRDY# active). After 150n seconds the CompactPCI bus is
available to the system for other CompactPCI bus activity. As the
CompactPCI bus is released, the ACPC8625 completes the read or
write cycle to the targeted IP module or carrier register within the
access times given in Table 2.5.
TABLE 2.5: ACPC8625 Write and Read Complete Time
Register Data Transfer Time
Carrier Registers Write 650nS, Typical
1
8 and 16-bit IP Write 750nS, Typical
1,2
32-bit IP Write 1250nS, Typical
1,3
Carrier Register Read 500nS, Typical
1
8 and 16-bit IP Read 650nS, Typical
1,2
32-bit IP Read 1100nS, Typical
1,3
Notes (Table 2.5):
1. The data transfer times given in table 2.5 are measured from the
falling edge of FRAME# to the falling edge of LRDYi#. The
CompactPCI bus starts a data transfer cycle by driving
FRAME# low. The ACPC8625 signals the completion of a read
or write cycle by driving LRDYi# low.
2. This access time assumes zero IP module wait states. For each
IP module wait state 125n seconds must be added to this value.
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