INDUSTRIAL I/O PACK SERIES ACPC8625 CompactPCI BUS CARRIER BOARD
___________________________________________________________________________________________
- 10 -
software determines which IP module to service first. In a
CompactPCI System interrupts are shared and can be from
any slot on the backplane. The routine must first check that
the interrupt came from the CompactPCI carrier by reading the
carrier interrupt pending register.
11. The interrupt service routine accesses the interrupt space of
the IP module selected to be serviced. Note that the interrupt
space accessed must correspond to the interrupt request
signal driven by the IP module.
12. The carrier board will assert the INTSEL* signal to the
appropriate IP together with (carrier board generated) address
bit A1 to select which interrupt request is being processed (A1
low corresponds to INTREQ0*; A1 high corresponds to
INTREQ1*).
13. The IP module receives an active INTSEL* signal from the
carrier and supplies its interrupt vector to the host system
during this interrupt acknowledge cycle. An IP module
designed to release its interrupt request on acknowledge will
release its request upon receiving an active INTSEL* signal
from the carrier. If the IP module is designed to release its
interrupt request on register access the interrupt service
routine must access the required register to clear the interrupt
request.
14. Write “End-Of-Interrupt” command to CPU’s 8259 (or
equivalent).
15. If the IP interrupt stimulus has been removed and no other IP
modules have interrupts pending, the interrupt cycle is
completed (i.e. the carrier board negates its interrupt request
INTA#).
4.0 THEORY OF OPERATION
This section describes the basic functionality of the circuitry
used on the carrier board. Refer to the Block Diagram shown in the
Drawing 4501-790 as you review this material.
CARRIER BOARD OVERVIEW
The carrier board is a CompactPCI bus slave/target board
providing up to four industry standard IP module interfaces. The
carrier board’s CompactPCI bus interface allows an intelligent single
board computer (CompactPCI bus Master) to control and
communicate with IP modules that are present on the CompactPCI
bus carrier. IP module field I/O connections link to the field I/O
connections of the carrier which in turn are used to connect field
electronic hardware to the carrier board via SCSI-2 cable and
TRANS-C200 transition module.
The CompactPCI bus and IP module logic commons have a
direct electrical connection (i.e., they are not electrically isolated).
However, the field I/O connections can be isolated from the PCI bus
if an IP module that provides this isolation (between the logic and
field side) is utilized. A wide variety of IP modules are currently
available (from Acromag and other vendors) that allow interface to
many external devices for digital I/O, analog I/O, and communication
applications.
CompactPCI Bus Interface
The carrier board’s CompactPCI bus interface is used to
program and monitor carrier board registers for configuration and
control of the board’s documented modes of operation (see section
3). In addition, the CompactPCI bus interface is also used to
communicate with and control external devices that are connected to
an IP module’s field I/O signals (assuming an IP module is present
on the carrier board).
The CompactPCI bus interface is implemented in the logic of
the carrier board’s CompactPCI bus target interface chip. The
CompactPCI bus interface chip implements PCI Specification
Version 2.1 and CompactPCI Specifications PICMG 2.0 R2.1 as an
interrupting slave including 8-bit and 16-bit data transfers to the IP
modules.
The carrier board’s CompactPCI bus data transfer rates are
shown in Table 2.5.
Carrier Board Registers
The carrier board registers (presented in section 3) are
implemented in the logic of the carrier board’s Field Programmable
Gate Array (FPGA). An outline of the functions provided by the
carrier board registers includes:
•
Monitoring the error signal received from each IP module is
possible via the IP Error Bit.
•
Enabling of CompactPCI bus interrupt requests from each IP
module is possible via the IP Module Interrupt Enable Bit.
•
Enabling of interrupt generation upon an IP module access
time out is implemented via the Time Out Interrupt Enable
Bit.
•
Monitoring an IP module access time out is possible via the IP
Module Access Time Out Status Bit.
•
Identify pending interrupts via the carrier’s IP Module
Interrupt Pending Bit.
•
Lastly, pending interrupts can be individually monitored via the
IP Module Interrupt Pending register.
IP Logic Interface
The IP logic interface is also implemented in the logic of the
carrier board’s FPGA. The carrier board implements ANSI/VITA 4
1995 Industrial I/O Pack logic interface specification and includes
four IP logic interfaces. The CompactPCI bus address and data
lines are linked to the address and data of the IP logic interface.
This link is implemented and controlled by the carrier board’s FPGA.
The CompactPCI bus to IP logic interface link allows a
CompactPCI bus master to:
•
Access up to 64 ID Space bytes for IP module identification via
8-bit or 16-bit data transfers using CompactPCI bus.
•
Access up to 128 I/O Space bytes of IP data via 8-bit or 16-bit
data transfers.
•
Access IP module interrupt space via 8-bit or 16-bit
CompactPCI bus data transfers.
•
Respond to two IP module interrupt requests per IP module.
Carrier Board Clock Circuitry
A 16MHz clock is divided down by a clock driver to obtain the IP
module 8MHz clock signals. Separate IP clocks are driven to each
IP module. All clock lines include series damping resistors to
reduce clock overshoot and undershoot.
When an IP module places data on the bus, for all data read
cycles, any undriven data lines are read by the CompactPCI bus as
high because of pull-up resisters on the carrier board’s data bus.
CompactPCI Interrupter
Interrupts are initiated from an interrupting IP module. However,
the carrier board will only pass an interrupt generated by an IP
module to the CompactPCI bus if the carrier board has been first
enabled for interrupts. Each IP module can initiate two interrupts
which can be individually monitored on the carrier board. After
interrupts are enabled on the carrier board via the Interrupt Enable
Bits (see section 3 for programming details), an IP generated
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
