INDUSTRIAL I/O PACK SERIES ACPC8625 CompactPCI BUS CARRIER BOARD
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BIT
FUNCTION
Write
IP module access. The default setting or reset
condition is “0” (interrupt generation upon time
out disabled). The interrupt service routine, in
responding to the Time Out Access interrupt, will
need to set this bit to 0 to clear the pending
interrupt request.
02
Read
and
Write
IP Module Interrupt Enable
When set to “1”, this bit will enable the generation
of IP module interrupts. The default setting or
reset condition is “0” (IP module interrupt
generation disabled). Interrupts must also be
supported and configured at the IPs.
01
Read
Only
IP Module Interrupt Pending
This bit will be "1" when there is an interrupt
pending. This bit will be "0" when there is no
interrupt pending. Polling this bit will reflect the
IP Module’s pending interrupt status, even if the
IP Module Interrupt Enable bit is set to "0".
Reset condition: Set to "0".
00
Read
Only
IP Module Error
This bit will be "1" when there is an active IP
Module Error signal. This bit will be "0" when all
IP module Error signals are inactive. This bit
allows the user to monitor the Error signals of IP
modules A through D. The Industrial I/O Pack
specification states that the error signals indicate
a non-recoverable error from the IP (such as a
component failure or hard-wired configuration
error). Refer to your IP specific documentation to
see if the error signal is supported and what it
indicates. Reset condition: Set to "0".
IP Interrupt Pending Register - (Read, Base + 02H)
The IP Interrupt Pending Register is used to individually identify
pending IP interrupts or a pending carrier generated interrupt as a
result of IP module time out access. If multiple IP interrupts are
pending, software must determine the order in which they are
serviced.
MSB
D7
D6
D5
D4
D3
D2
D1
LSB
D0
IP D
Int1
Pend
IP D
Int0
Pend
IP C
Int1
Pend
IP C
Int0
Pend
IP B
Int1
Pend
IP B
Int0
Pend
IP A
Int1
Pend
IP A
Int0
Pend
MSB
D15
D14
D13
D12
D11
D10
D9
LSB
D8
Not
Used
Time Out
Interrupt
Pend
Not
Used
Not
Used
Where:
All Bits
IP Interrupt Pending
(Read)
A bit will be a “1” when the corresponding
interrupt is pending. A bit will be a “0” when
its corresponding interrupt is not pending.
Polling this bit will reflect the IP module’s
pending interrupt status, even if the IP
interrupt enable bit is set to “0”.
Reset Condition: Set to "0". An IP module
pending interrupt bit will be cleared if its
corresponding interrupt request signal is
inactive.
IP Module Interrupt Space - (Read Only)
The Interrupt space for each IP module is fixed at two 16-bit
words. Interrupt 0 select space is read, typically by an interrupt
service routine, to respond to an interrupt request via the IP
Module’s INTREQ0* signal. Likewise interrupt 1 select space is
read to respond to an interrupt request via the IP Module’s
INTREQ1* signal. An access to an interrupt select space results in
the IP module serving up an interrupt vector. In addition, access to
the interrupt space will cause some IP modules to release their
interrupt request. See each IP module’s User Manual for details.
IP Module ID Space - (Read Only)
Each IP contains identification (ID) information that resides in
the ID space per the IP specification. This area of memory contains
either 32 bytes (Format I ID) or 64 bytes (Format II ID) of
information, at most. Format I requires read of only the least
significant byte. Format II requires read of a 16-bit value. The
carrier will implement 16-bit reads to the ID space to allow support
for either Format I or Format II. Both fixed and variable information
may be present within the ID ROM. Variable information may
include unique information required for the module. The
identification Section for each IP module is located in the carrier
board memory map per Table 3.3. Refer to the documentation of
your IP module for specific information about each IP module’s ID
Space contents.
IP Module I/O Space - (Read/Write Only, 256-Byte Addresses)
The I/O space on each IP module is fixed at 128, 16-bit words
(256 bytes). The four IP module I/O spaces are accessible at fixed
offsets for the ACPC8625’s Base Address. IP modules may not
fully decode their I/O space and may use byte or word only
accesses. See each IP module’s User Manual for details.
GENERATING INTERRUPTS
Interrupt requests originate from the carrier board in the case of
an access time out and from the IP modules. Each IP may support
0, 1, or 2 interrupt requests. Upon an IP module interrupt request
the carrier passes the interrupt request on to the host, provided that
the carrier board is enabled for interrupts within the Carrier Board
Status Register.
Sequence of Events For an Interrupt
1. Clear the interrupt enable bits in the Carrier Board Status
Register by writing a "0" to bit 2/bit 3.
2. Write interrupt vector to the location specified on the IP and
perform any other IP specific configuration required - do for
each supported IP interrupt request.
3. Determine the IRQ line assigned to the carrier during system
configuration (within the configuration register).
4. Set up the CPU’s interrupt vector for the appropriate interrupt.
5. Unmask the IRQ on the CPU’s 8259 (or equivalent) interrupt
controller.
6. The IP asserts an interrupt request to the carrier board (asserts
interrupt request line IntReq0* or IntReq1*).
7. The carrier drives PCI bus interrupt request signal INTA#
active.
8. CPU drives the IRQ line assigned to the active carrier.
9. The interrupt service routine pointed to by the vector set up in
step 4 starts.
10. Interrupt service routine determines which IP module caused
the interrupt by reading the carrier interrupt pending register. If
multiple interrupts are pending the interrupt service routine
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