Abov MC96FM204, Руководство пользователя

Страница: 83 / 172

MC96FM204/FM214
April 7, 2016 Ver. 1.8 83
11.2.3 Register Map
Table 11-2 Basic Interval Timer Register Map
Name Address Dir Default Description
BITCNT 8CH R 00H Basic Interval Timer Counter Register
BITCR 8BH R/W 01H Basic Interval Timer Control Register
11.2.4 Basic Interval Timer Register Description
The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval
timer control register (BITCR). If BCLR bit set t
o ‘1’, BITCNT becomes ‘0’ and then counts up. After 1 machine
cycle, BCLR bit is cleared to
‘0’ automatically.
11.2.5 Register Description for Basic Interval Timer
BITCNT (Basic Interval Timer Counter Register) : 8CH
7 6 5 4 3 2 1 0
BITCNT7 BITCNT6 BITCNT5 BITCNT4 BITCNT3 BITCNT2 BITCNT1 BITCNT0
R R R R R R R R
Initial value : 00H
BITCNT[7:0] BIT Counter
BITCR (Basic Interval Timer Control Register) : 8BH
7 6 5 4 3 2 1 0
BITIFR
– – –
BCLR BCK2 BCK1 BCK0
R/W
– – –
R/W R/W R/W R/W
Initial value : 01H
BITIFR When BIT Interrupt occurs, this bit becomes
‘1’. For clearing bit, write ‘0’
to this bit or auto clear by INT_ACK signal.
0 BIT interrupt no generation
1 BIT interrupt generation
BCLR If this bit is written to
‘1’, BIT Counter is cleared to ‘0’
0 Free Running
1 Clear Counter
BCK[2:0]
Select BIT overflow period
BCK2 BCK1 BCK0 Description
0 0 0 Bit 0 overflow (BIT Clock * 2)
0 0 1 Bit 1 overflow (BIT Clock * 4) (default)
0 1 0 Bit 2 overflow (BIT Clock * 8)
0 1 1 Bit 3 overflow (BIT Clock * 16)
1 0 0 Bit 4 overflow (BIT Clock * 32)
1 0 1 Bit 5 overflow (BIT Clock * 64)
1 1 0 Bit 6 overflow (BIT Clock * 128)
1 1 1 Bit 7 overflow (BIT Clock * 256)