Theory of Operation
Halt with Interrupt Restart
To further decrease power consumption from the Clock Slowdown
mode described above, the processor clock may be halted during
times processing is not needed, and restarted by an interrupt. This
interrupt may be from an external source, such as an event requiring
service from the processor, or from one of the on-board timers. Since
the three 16-bit timers on board are driven by an independent
oscillator, the timers continue to run at their full 1.19 MHz frequency
and are not affected by a stopped processor clock. Alternatively, the
timer clock inputs could count external events and interrupt the
processor upon reaching a predetermined count. Any counters not
initialized remain idle and do not affect power consumption.
The mechanism used to stop and restart the processor clock is a part
of the 82C85 clock chip supplied on the ZT 88CT08A and
ZT 88CT09A boards only. This chip monitors the status lines from
the CPU. When a processor halt status is seen on those status lines,
the 82C85 halts its clock output. This in turn stops the processor.
When an interrupt is seen out of the 82C59A Programmable Interrupt
Controller on board, the 82C85 then restarts the clock.
Functional Differences
The following should be kept in mind regarding power consumption.
The CMOS logic is rated for a typical and a maximum power
consumption (see Appendix B).
Notice that maximum power
consumption is generally seen at the higher operating temperatures.
This temperature variance affects battery life as well: the lower the
temperature, the longer the battery life. The minimum battery life
detailed previously in this chapter is generally seen at +65˚ Celsius. If
operating this board at +85˚ C, this value should generally hold since
all I.C. specifications cover up to +85˚ C.
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