Specifications
CLOCK*
(1)
BUSRQ*
DBUS
D0-D7
tD23
tD21
CPU USE
BUSAK*
tD22
CPU USE
tD24
tD25
DMA USE
A0-A15
CPU USE
CPU USE
(2)
CONTROL
tD27
DMA USE
DMA USE
CPU USE
CPU USE
tD26
tD28
SYMBOL
PARAMETER
MIN MAX
MAX
MAX
MAX
MIN
MIN
MIN
tD21
tD22
tH23
tD24
tD25
tD26
tD27
tD28
All times given in nanoseconds
Delay from CLOCK* to BUSAK* low
Delay from CLOCK* to BUSAK* high
Delay from BUSAK* to Data Bus 3-State
Delay from BUSAK* to Data Bus driven
Delay from BUSAK* to Address Bus 3-State
Delay from BUSAK* to Address Bus driven
Delay from BUSAK* to Control Bus 3-State
Delay from BUSAK* to Control /bus driven
12
0
161
2
0
40
178
11
38
11
12
0
86
2
0
40
81
11
38
11
14
0
134
0
0
60
178
9
44
8
14
0
59
0
0
60
81
9
44
8
ZT 8808A
ZT 8809A
ZT 88CT08A ZT 88CT09A
Figure B–13. ZT 8809A Bus Exchange Timing.
B-28
