ILLUSTRATIONS
Figure 1–1
ZT 8809A Functional Block Diagram.
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1-5
Figure 2–1
Non-DOS Factory Default Jumper Configuration.
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2-8
Figure 2–2
ZT 8809A Configured For STD DOS.
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2-14
Figure 2–3
STD DOS Factory Default Memory Map.
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2-20
Figure 2–4
STD ROM Factory Default Memory Map.
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2-21
Figure 2–5
I/O Map, STD DOS / STD ROM Systems.
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2-23
Figure 3–1
PIC Interrupt Input Requests.
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3-9
Figure 3–2
Polled Interrupt Structure.
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3-11
Figure 3–3
Small Scale Vectored Structure.
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3-12
Figure 3–4
Large Scale Vectored Structure.
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3-13
Figure 3–5
DMA With STD Bus Controller.
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3-17
Figure 3–6
AC Transformer Connection.
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3-19
Figure 5–1
STD DOS Factory Default Memory Map.
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5-4
Figure 5–2
STD DOS Factory Default Jumper Configuration.
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5-5
Figure 5–3
STD DOS Map with 640K On-Board RAM.
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5-6
Figure 5–4
STD DOS With 640K RAM Jumper Configuration.
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5-7
Figure 5–5
Non-DOS Factory Default Memory Map.
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5-8
Figure 5–6
Non-DOS Factory Default Jumper Configuration.
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5-9
Figure 5–7
Memory Chip Locations.
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5-11
Figure 5–8
ZT 8809A I/O Map.
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5-16
Figure 6–1
Program Status Word.
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6-8
Figure 6–2
V20 Modes.
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6-13
Figure 6–3
DMA With STD Bus Controller.
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6-19
Figure 7–1
zSBC 337 Piggyback Processor Installation.
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7-6
Figure 8–1
Establishing Serial Communications.
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8-5
Figure 8–2
Loopback of RTS/CTS, DTR/DSR.
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8-7
Figure 8–3
16C452 Serial Port Block Diagram.
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8-9
Figure 9–1
Printer Interface Block Diagram.
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9-2
Figure 10–1
Real-Time Clock Block Diagram.
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10-2
Figure 10–2
Timechip Comparison Register.
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10-5
Figure 10–3
Timechip Register.
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10-7
Figure 11–1
Intel 8254 Timers Block Diagram.
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11-3
Figure 11–2
Internal Block Diagram of a Counter.
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11-4
