< Features and System Configuration >
1-14
TI 34M6A82-01E
2nd Edition : Nov. 1, 2002-00
1.4.2 Ladder Sequence Device Performance Specifications
Table
List of devices
F3SP28-3N/-3S
F3SP53-4H/-4S
F3SP38-6N/-6S
F3SP58-6H/-6S
F3SP59-7S
Device Name
Range
No. of
points
Range
No. of
points
Range
No. of
points
Remarks
Input relay
X
X00201 to
X71664 (not
continuous)
X00201 to
X71664 (not
continuous)
X00201 to
X71664 (not
continuous)
Output relay
Y
Y00201 to
Y71664 (not
continuous)
4096
Y00201 to
Y71664 (not
continuous)
8192
Y00201 to
Y71664 (not
continuous)
8192
Available ranges
depend on specific
modules
Internal relay
I
I00001 to
I16384
16384 I00001 to
I32768
32768 I00001 to
I65535
65535
Shared relay
E0001 to
E2048
2048 E0001 to
E2048
2048 E0001 to
E2048
2048
Extended
shared relay
Non-
lock-up
type
E
E2049 to
E4096
2048 E2049 to
E4096
2048 E2049 to
E4096
2048
The default is 0.
Configuration is
required when using
multiple CPU
modules.
Link relay
Non-
lock-up
type
L
L0001 to
L72048 (not
continuous)
8192
L0001 to
L72048 (not
continuous)
16384
L0001 to
L72048 (not
continuous)
16384 Used for FA link
communications
Special relay
M
M0001 to
M9984
9984 M0001 to
M9984
9984 M0001 to
M9984
9984
100 µs
timer
T0001 to
T0016
T0001 to
T0016
T0001 to
T0016
Up to 16 timers can
be set up
1 ms
timer
10 ms
timer
Timer
100 ms
timer
Continuous
timer
100 ms
timer
T
T0001 to
T2048
T0001 to
T3072
T0001 to
T3072
The number of timers
available depends on
the number of
counters used (C)
(see note)
Counter
Lock-up
type
C
C0001 to
C2048
Total
2048
C0001 to
C3072
Total
3072
C0001 to
C3072
Total
3072
The number of
counters available
depends on the
number of timers
used (T) (see note)
Data register Lock-up
type
D
D00001 to
D16384
16384 D00001 to
D32768
32768 D00001 to
D65535
65535
File register
Lock-up
type
B
B000001 to
B32768
32768 B000001 to
B262144
262144 B000001 to
B262144
262144
Link register
Non-
lock-up
type
W
W00001 to
W72048
(not
continuous)
8192
W00001 to
W72048
(not
continuous)
16384
W00001 to
W72048
(not
continuous)
16384 Used for FA link
communications
Special register
Z
Z0001 to
Z1024
1024 Z0001 to
Z1024
1024 Z0001 to
Z1024
1024
Index register
V
V001 to
V256
256 V001 to
V256
256 V001 to
V256
256
Shared
register
R0001 to
R1024
1024 R0001 to
R1024
1024 R0001 to
R1024
1024
Extended
shared
register
Non-
lock-up
type
R
R1025 to
R4096
3072 R1025 to
R4096 3072
R1025 to
R
4096 3072
The default is 0.
Configuration is
required when using
multiple CPU
modules.
Note: See “Device Capacities and Configuration Limits” on page 1-15.
