Appendix D
Master Constraints File Listing
The Xilinx design constraints (XDC) file template for the ZCU1285 board provides for designs
targeting the Zynq Ult RFSoC ZCU1285 characterization kit. Net names in the listed
constraints correlate with net names on the ZCU1285 board schematic. Identify the appropriate
pins and replace the following net names with net names in the user RTL. See the Vivado Design
Suite User Guide: Using Constraints (
) for more information.
See the boards file on the
ZCU1285 Characterization Kit documentation
website for the latest
version of the FPGA XDC file.
Appendix D: Master Constraints File Listing
UG1348 (v1.0) July 16, 2019
ZCU1285 Board User Guide
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