PLL B and C
PLL B and C have two differential output SMA pairs each that are used as RF sampling clocks for
RF-DACs. Each PLL is programmable to any frequency up to 6.4 GHz with a phase noise
performance of -130 dBc/Hz at 1 MHz offset from the carrier and individually programmable
output power levels up to 6 dBm. The default boot frequency for each of these PLLs is 4.9152
GHz and a typical output power level is 4 dBm.
General Purpose Clocks
The general-purpose clocks are three pairs of phase-aligned LVDS clocks (SYS_REF_1,
SYS_REF_2, and FPGA_REF_CLK) programmable to any frequency up to 1.0 GHz. Each clock pair
can be individually enabled or disabled. The default boot state for these clocks is disabled.
Single-Ended Reference Clock
The single-ended reference clock is an LVCMOS output that can be enabled or disabled, and is
programmable to any frequency up to 250 MHz. The default boot frequency for this clock is 12.8
MHz.
Programming the Clocks
The clocks on the SuperClock-RF2 Module can be programmed using the System Controller user
interface (SCUI). See
. A set of clock files are provided along with
the System Controller user interface. The clock files contain PLL register values used to program
the clocks to a pre-set frequency. To create custom clock files, contact
.
SuperClock-RF2 Pin Mapping
The SuperClock-RF2 Module maps to RFSoC I/O by way of two I2C signals. The following table
lists the RFSoC I/O mapping for the SuperClock-RF2 Module interface. To connect to the
SuperClock-RF2 Module using the I2C bus, see
.
Table 20: RFSoC PS to UART Connection
RFSoC (U1)
Schematic Net
Name
J170 Pin
Pin
Function
Direction
IOSTANDAR
D
Pin
Function
Direction
AM26
Control I/O
Bidir
LVCMOS
ACM_SCL/
DUT_PMBUS_CLK
62
I2C
Bidir
AP23
Control I/O
Bidir
LVCMOS
ACM_SDA/
DUT_PMBUS_DATA
64
I2C
Bidir
Chapter 1: ZCU1285 Board Features and Operation
UG1348 (v1.0) July 16, 2019
ZCU1285 Board User Guide
40
