Xilinx ZCU1285, User Manual

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Table 17: PS-GTR Transceiver Reference Clock Inputs (cont'd)
RFSoC (U1) Net Name Bank Connector
AD35 PS_REFCLK1_N 505 J39
AC36 PS_REFCLK2_P 505 J194
AC37 PS_REFCLK2_N 505 J156
AB34 PS_REFCLK3_P 505 J158
AB35 PS_REFCLK3_N 505 J159
SuperClock-2 Module
The SuperClock-2 Module (callout 6, Figure 2: Board Component Locations ) connects to the
clock module interface connector (J36) and provides a programmable, low-noise and low-jitter
clock source for use with the GTY and PS-GTR transceivers. The clock module maps to the
RFSoC by way of two I2C signals, two LVDS pairs, and one global clock pair. The following table
lists the RFSoC mapping for the SuperClock-2 Module interface. To program the SuperClock-2
Module using the System Controller, see
Appendix E: System Controller . To connect to the
SuperClock-2 Module using the I2C bus, see I2C Bus Management .
Table 18: SuperClock-2 Interface Connections
RFSoC (U1)
Schematic Net
Name
J36 Pin
Pin Function Direction
IOSTANDAR
D
Pin Function Direction
L28 Clock recovery Input LVDS CM_LVDS1_P 1 Clock recovery Output
L29 Clock recovery Input LVDS CM_LVDS1_N 3 Clock recovery Output
H10 Clock recovery Input LVDS CM_LVDS2_P 9 Clock recovery Output
H9 Clock recovery Input LVDS CM_LVDS2_N 11 Clock recovery Output
AP24 Global clock Input LVDS CM_GCLK_P 25 Global clock Output
AR24 Global clock Input LVDS CM_GCLK_N 27 Global clock Output
AM26 Control I/O Bidir LVCMOS CM_I2C_SCL/
DUT_PMBUS_CLK
62 I2C Bidir
AP23 Control I/O Bidir LVCMOS CM_I2C_SDA/
DUT_PMBUS_DATA
64 I2C Bidir
Chapter 1: ZCU1285 Board Features and Operation
UG1348 (v1.0) July 16, 2019 www.xilinx.com
ZCU1285 Board User Guide 37
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