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Xilinx ZC702, User Manual

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Xilinx ZC702 User Manual Download Page 51

ZC702 Board User Guide

www.xilinx.com

51

UG850 (v1.2) April 4, 2013

Feature Descriptions

PS_SRST_B:

 This reset is used to force a system reset. It can be tied or pulled High, and can 

be High during the PS supply power ramps.

Refer to 

UG585

, 

Zynq-7000 All Programmable SoC Technical Reference Manual 

for 

information concerning the resets.

FPGA Mezzanine (FMC) Card Interface

[

Figure 1-2

, callout 

24

]

The ZC702 board supports the VITA 57.1 FPGA Mezzanine Card (FMC) specification by 
providing subset implementations of low pin count (LPC) connectors at J3 and J4. Both 
connectors use a 10 x 40 form factor that is partially populated with 160 pins. The 
connectors are keyed so that a the mezzanine card faces away from the ZC702 board when 
connected.

Signaling Speed Ratings:

•

Single-ended: 9 GHz (18 Gb/s)

•

Differential Optimal Vertical: 9 GHz (18 Gb/s)

•

Differential Optimal Horizontal: 16 GHz (32 Gb/s)

•

High Density Vertical: 7 GHz (15 Gb/s)

The Samtec connector system is rated for signaling speeds up to 9 GHz (18 Gb/s) based on 
a –3 dB insertion loss point within a two-level signaling environment.

Connector Type:

•

Samtec SEAF Series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector

For more information about SEAF series connectors, go to the Samtec website 

[Ref 13]

.

LPC Connectors J3 and J4

[

Figure 1-2

, callout 

24

]

The 160-pin LPC connector defined by the FMC specification (

Figure B-1, page 65

) provides 

connectivity for up to:

•

68 single-ended or 34 differential user-defined signals (34 LA pairs, LA00–LA33)

•

1  GTX  transceiver

•

1  GTX  clock

•

2 differential clocks

•

61 ground and 10 power connections

Summary of Contents for ZC702

Page 1: ...ZC702 Evaluation Board for the Zynq 7000 XC7Z020 All Programmable SoC User Guide UG850 v1 2 April 4 2013...

Page 2: ...ility for use of Xilinx products in Critical Applications http www xilinx com warranty htm critapps Automotive Applications Disclaimer XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL SAFE OR F...

Page 3: ...nd QSPI section of UG585 JTAG information in Figure 1 10 and Table 1 10 was updated In Figure 1 10 pin numbers 5 and 6 are swapped and in U76 IN2 and IN1 switched places In Table 1 10 SW10 became SW10...

Page 4: ...mmable Logic JTAG Programming Options 25 Programmable Logic JTAG Select Switch JTAG Cable Connector 25 FMC Connector JTAG Bypass 27 Clock Generation 27 System Clock 28 Programmable User Clock 28 Proce...

Page 5: ...ppendix A Default Switch and Jumper Settings Switches 63 Jumpers 63 Appendix B VITA 57 1 FMC Connector Pinouts Appendix C Master UCF Listing Overview 66 ZC702 Board UCF Listing 66 Appendix D Board Spe...

Page 6: ...ZC702 Board User Guide www xilinx com 6 UG850 v1 2 April 4 2013 Electromagnetic Compatibility 76 Safety 77 Markings 77...

Page 7: ...VITA 57 FPGA mezzanine cards FMC attached to either of two low pin count LPC FMC connectors ZC702 Board Features The ZC702 board features are listed in here Detailed information for each feature is p...

Page 8: ...ser I O Two programmable logic PL user pushbuttons PL user DIP switch 2 pole Eight PL user LEDs Two processing system PS pushbuttons shared with PS 2 pole DIP switch Two PS user LEDs Dual row Pmod GPI...

Page 9: ...and Connector Page 15 Quad SPI Flash Memory Page 20 CAN Bus Page 21 SD Card Connector Page 22 FMC1 LPC Connector Page 23 10 100 1 000 Ethernet PHY RGMII only Page 26 USB 2 0 ULPI Transceiver and Conn...

Page 10: ...ons starting on page 12 CAUTION The ZC702 board can be damaged by electrostatic discharge ESD Follow ESD prevention measures when handling the board X Ref Target Figure 1 2 Figure 1 2 ZC702 Board Comp...

Page 11: ...ock 200 MHz 2 5V LVDS oscillator SiTime SIT9102 243N25E200 0000 30 8 U28 U65 Programmable User Clock and Processing System Clock Source Silicon Labs SI570BAB0000544DG default 156 250MHz PS fixed 33 MH...

Page 12: ...1420 15 24 J3 J4 FPGA Mezzanine FMC Card Interface Samtec ASP_134486_01 23 24 25 U32 U33 U34 Power Management bottom and top of board TI UCD9248PFC in conjunction with various regulators 39 47 26 J40...

Page 13: ...I2C CAN UART and GPIO The PS runs independently of the PL and boots at power up or reset A system level block diagram is shown in Figure 1 4 X Ref Target Figure 1 3 Figure 1 3 High Level Block Diagram...

Page 14: ...get Figure 1 4 Figure 1 4 Zynq 7000 AP SoC Block Diagram 2x USB 2x GigE 2x SD Zynq 7000 AP SoC I O Peripherals IRQ IRQ EMIO SelectIO Resources DMA 8 Channel CoreSight Components Programmable Logic DAP...

Page 15: ...al Reference Manual Encryption Key Backup Circuit The XC7Z020 AP SoC U1 implements bitstream encryption key technology The ZC702 board provides the encryption key backup battery circuit shown in Figur...

Page 16: ...age Connected To PL Bank 0 VCC2V5_PL 2 5V AP SoC Configuration Bank 0 PL Bank 13 VADJ 1 2 5V FMC2 GPIO PL_PJTAG IIC_MAIN PL Bank 33 FMC2 HDMI Codec PL Bank 34 FMC1 HDMI Codec PL Bank 35 FMC1 HDMI Code...

Page 17: ...AP SoC XC7Z020 U1 Pin Net Name Component Memory Pin Number Pin Name Reference Designator E3 PS_DDR3_DQ0 B3 DQ0 U66 C3 PS_DDR3_DQ1 C7 DQ1 U66 F2 PS_DDR3_DQ2 C2 DQ2 U66 D1 PS_DDR3_DQ3 C8 DQ3 U66 F1 PS_...

Page 18: ...2 PS_DDR3_DM3 B7 DM3 U69 V2 PS_DDR3_DQS3_P C3 DQS3_P U69 W2 PS_DDR3_DQS3_N D3 DQS3_N U69 M4 PS_DDR3_A0 K3 A0 U66 U67 U68 U69 M5 PS_DDR3_A1 L7 A1 U66 U67 U68 U69 K4 PS_DDR3_A2 L3 A2 U66 U67 U68 U69 L4...

Page 19: ...ber N25Q128A11ESF40G Micron Numonyx Supply voltage 1 8V Data path width 4 bits Data rate Various depending on Single Dual Quad mode G4 PS_DDR3_A14 N7 A14 U66 U67 U68 U69 L7 PS_DDR3_BA0 J2 BA0 U66 U67...

Page 20: ...to the XC7Z020 AP SoC XC7Z020 U1 Schematic Net Name Quad SPI Flash Memory U41 MIO Select Header Pin Name Bank Pin Number Pin Number Pin Name PS_MIO6 500 A4 QSPI_CLK 16 C J26 2 PS_MIO5 500 A3 QSPI_IO3...

Page 21: ...emented through the IP in the XC7Z020 AP SoC Processor System Table 1 6 describes the jumper settings for the USB 2 0 circuit The connections between the USB Mini B connector at J1 and the PHY at U9 a...

Page 22: ...U1 Schematic Net Name USB3320 U9 Pin Pin Name Bank Pin Number PS_MIO36 501 A9 USB_CLKOUT 1 PS_MIO31 501 F9 USB_NXT 2 PS_MIO32 501 C7 USB_DATA0 3 PS_MIO33 501 G13 USB_DATA1 4 PS_MIO34 501 B12 USB_DATA2...

Page 23: ...ATA7_13 DATA1_4 SPK_L_15 REFCLK_26 SPK_R_16 XO_25 VDD18_30 DATA3_6 STP_29 VDD18_28 RESETB_27 CTR_GND_33 SHLD5 SHLD6 GND SHLD4 VBUS D_N D_P SHLD1 SHLD2 SHLD3 ID 1 2 DEVICE MODE OFF DEVICE MODE 2 3 HOST...

Page 24: ...2 5 1 10W 4 7K R321 18 13 14 15 2 3 5 6 7 8 9 1 10 4 11 12 16 17 J64 67840 8001 22 SDIO_CLK VCC3V3 1 2 C27 0 1 F 25V X5R SDIO_DAT2 22 SDIO_DAT0 22 22 SDIO_DAT1 SDIO_CD_DAT3 22 22 SDIO_CMD Table 1 9 S...

Page 25: ...3 to 1 analog switch U75 U76 and U77 controlled by a 2 position DIP switch at SW10 Figure 1 10 shows the JTAG analog switches and DIP switch SW10 X Ref Target Figure 1 9 Figure 1 9 JTAG Chain Block Di...

Page 26: ...switch settings are shown in Table 1 10 X Ref Target Figure 1 10 Figure 1 10 PL JTAG Programming Source Analog Switch UG850_c1_10_030513 SDA02H1SBD SW10 VCC3V3 4 3 JTAG_SEL_1 JTAG_SEL_2 R375 4 7kW 0 1...

Page 27: ...1 12 lists the pin to pin connections from each clock source to the XC7Z020 AP SoC Table 1 10 Switch SW10 JTAG Configuration Option Settings Configuration Source DIP Switch SW10 1 2 Switch 1 1 JTAG_SE...

Page 28: ...low jitter 3 3V LVDS differential oscillator U28 connected to the MRCC inputs of bank 13 This USRCLK_P and USRCLK_N clock signal pair is connected to XC7Z020 AP SoC U1 pins Y9 and Y8 respectively On...

Page 29: ...ixed 33 33333 MHz oscillator at U65 It is wired to PS bank 500 pin F7 PS_CLK on the XC7Z020 AP SoC Oscillator SiTime SiT8103AC 23 18E 33 33333 33 3 MHz Frequency jitter 50 ppm Single ended output For...

Page 30: ...ing the settings shown in Table 1 13 These settings can be overwritten via software commands passed over the MDIO interface X Ref Target Figure 1 13 Figure 1 13 Processing System Clock Source Table 1...

Page 31: ...Bank Pin Number Pin Name PS_MIO53 501 C12 PHY_MDIO 45 MDIO PS_MIO52 501 D10 PHY_MDC 48 MDC PS_MIO16 501 D6 PHY_TX_CLK 60 TX_CLK PS_MIO21 501 F11 PHY_TX_CTRL 63 TX_CTRL PS_MIO20 501 A8 PHY_TXD3 62 TXD3...

Page 32: ...20 AP SoC supports the USB to UART bridge using two signal pins Transmit TX and Receive RX Silicon Labs provides royalty free Virtual COM Port VCP drivers for the host computer These drivers permit th...

Page 33: ...DMI transmitter at U40 The HDMI output is provided on a Molex 500254 1927 HDMI type A receptacle at P1 The ADV7511 supports 1080P 60Hz YCbCr 4 2 2 encoding via 16 bit input data mapping The ZC702 boar...

Page 34: ...5 34 41 29 99 100 23 18 20 22 27 31 37 75 47 26 76 77 49 19 1 30 U40 ADV7511 VADJ HDMI_HEAC_C_N HDMI_AVDD HDMI_PLVDD HDMI_PLVDD 2 1 X5R 25V 0 1 F C78 HDMI_CLK HDMI_HSYNC HDMI_VSYNC HDMI_INT 1 1 1 10W...

Page 35: ...AA22 HDMI_D3 85 D11 V19 HDMI_D4 84 D12 V18 HDMI_D5 83 D13 V20 HDMI_D6 82 D14 U20 HDMI_D7 81 D15 W21 HDMI_D8 80 D16 W20 HDMI_D9 78 D17 W18 HDMI_D10 74 D18 T19 HDMI_D11 73 D19 U19 HDMI_D12 72 D20 R19 H...

Page 36: ...es must first set up a path to the desired bus through the U44 bus switch at I2C address 0x74 0b01110100 Table 1 19 lists the address for each bus 33 HDMI_CLK_P 10 32 HDMI_CLK_N 12 54 HDMI_DDCSDA 16 5...

Page 37: ...nctions Programming information for the RTC 8564JE is available in the RTC 8564JE NB Application Manual at the Epson Electronics America website Ref 9 Figure 1 17 shows the real time clock circuit Tab...

Page 38: ...ilent website for information on Digilent Pmod Peripheral Modules Ref 10 The expansion header circuit is shown in Figure 1 18 X Ref Target Figure 1 17 Figure 1 17 Real Time Clock Circuit Table 1 20 Re...

Page 39: ...Figure 1 19 shows the controller area network CAN bus interface X Ref Target Figure 1 18 Figure 1 18 I O Expansion Header Circuit UG850_c1_18_030513 GND IIC_PORT_EXPANDER_SDA TCA641APWR 16 Bit I2 C an...

Page 40: ...2 3 TXS0104E Bidirectional Voltage Level Translator U3 14 13 12 11 A2 A1 VCCA B3 B2 B1 VCCB 10 9 8 4 5 6 NC1 A4 A3 7 GND VCCMIO GND C24 0 1 F 25V X5R GND C520 47 F 10V X5R GND CAN TXD CAN RXD CAN STB...

Page 41: ...The data sheet and other product information for the Marvell 88E1116R Alaska Gigabit Ethernet Transceiver is available at the Marvell website Ref 7 Table 1 22 Status LEDs Reference Designator Net Name...

Page 42: ...P_SW1 and GPIO_DIP_SW0 SW12 User PS switches near callout 18 Pushbutton SW13 wired in parallel to DIP switch SW15 switch 1 Pushbutton SW14 wired in parallel to DIP switch SW15 switch 2 PS Power On and...

Page 43: ...s User LEDs Figure 1 2 callout 17 The ZC702 board supports eight user LEDs connected to XC7Z020 AP SoC Banks 13 33 34 and 35 via level shifters Note that the LEDs are wired in parallel with headers J6...

Page 44: ...NDS331N 460 mW DS17 VCC3V3 PMOD2 1 R406 261 0 1W GND 1 3 2 Q17 NDS331N 460 mW DS20 VCC3V3 PMOD1 1 R410 261 0 1W GND 1 3 2 Q14 NDS331N 460 mW DS16 VCC3V3 PMOD2 2 R405 261 0 1W GND 1 3 2 Q18 NDS331N 46...

Page 45: ...oC U1 Pin Net Name LED Reference E15 PMOD1_0 DS19 D15 PMOD1_1 DS20 W17 PMOD1_2 DS21 W5 PMOD1_3 DS22 V7 PMOD2_0 DS18 W10 PMOD2_1 DS17 P18 PMOD2_2 DS16 P17 PMOD2_3 DS15 G7 PS_LED1 DS23 E5 PS_MIO8_LED0 D...

Page 46: ...P SoC U1 User PS Switches Figure 1 2 near callout 18 Figure 1 25 shows the user PS pushbutton and DIP switch circuit X Ref Target Figure 1 23 Figure 1 23 GPIO DIP Switch Table 1 25 GPIO DIP Switch Con...

Page 47: ...connected to AP SoC Bank 13 GPIO pins which simultaneously drive J41 and J63 When J41 is used for ARM PJTAG functionality the J63 even numbered pin should not be used When J63 even numbered pins are u...

Page 48: ...e switch actuator from the Off to On position applies 12V power from J60 a 6 pin mini fit connector Green LED DS14 illuminates when the ZC702 board power is on See Power Management for details on the...

Page 49: ...Pushbutton Figure 1 2 callout 22 Switch SW4 grounds the XC7Z020 AP SoC PROG_B pin when pressed This action clears programmable logic configuration which the PS software can then act on The FPGA_PROG_B...

Page 50: ...gure 1 27 Figure 1 27 PROG_B Pushbutton SW4 UG850_c1_27_030513 FPGA PROG B VCC2V5 R51 4 7k 0 1 W 5 GND 2 1 3 4 SW4 To XC7Z020 AP SoC PROGRAM_B_0 U1 T11 X Ref Target Figure 1 28 Figure 1 28 PS Power On...

Page 51: ...rd faces away from the ZC702 board when connected Signaling Speed Ratings Single ended 9 GHz 18 Gb s Differential Optimal Vertical 9 GHz 18 Gb s Differential Optimal Horizontal 16 GHz 32 Gb s High Den...

Page 52: ...TL1_VCC4A_PG C3 NC D4 NC C6 NC D5 NC C7 NC D8 FMC1_LPC_LA01_CC_P N19 C10 FMC1_LPC_LA06_P J18 D9 FMC1_LPC_LA01_CC_N N20 C11 FMC1_LPC_LA06_N K18 D11 FMC1_LPC_LA05_P N17 C14 FMC1_LPC_LA10_P L17 D12 FMC1_...

Page 53: ...LPC_LA11_P R20 G19 FMC1_LPC_LA16_N P15 H17 FMC1_LPC_LA11_N R21 G21 FMC1_LPC_LA20_P G20 H19 FMC1_LPC_LA15_P P20 G22 FMC1_LPC_LA20_N G21 H20 FMC1_LPC_LA15_N P21 G24 FMC1_LPC_LA22_P G17 H22 FMC1_LPC_LA19...

Page 54: ...19 FMC2_LPC_LA14_N U22 D17 FMC2_LPC_LA13_P V22 C22 FMC2_LPC_LA18_CC_P AA9 D18 FMC2_LPC_LA13_N W22 C23 FMC2_LPC_LA18_CC_N AA8 D20 FMC2_LPC_LA17_CC_P AA7 C26 FMC2_LPC_LA27_P AB2 D21 FMC2_LPC_LA17_CC_N A...

Page 55: ..._LPC_LA11_P Y14 G19 FMC2_LPC_LA16_N AB15 H17 FMC2_LPC_LA11_N AA14 G21 FMC2_LPC_LA20_P T4 H19 FMC2_LPC_LA15_P Y13 G22 FMC2_LPC_LA20_N U4 H20 FMC2_LPC_LA15_N AA13 G24 FMC2_LPC_LA22_P U10 H22 FMC2_LPC_LA...

Page 56: ...ard Power Regulators VCCPINT VCCAUX VCCPAUX VCCADJ VCC1V5 VCCBRAM J60 12 V VCCMIO VCCINT VCC3V3 VCC2V5 Power Controller 2 Aux PMBus Address 53 Switching Regulator 1 5V at 10A U19 Switching Regulator 2...

Page 57: ...re Addr 52 39 PTD08D210W VoutA U17 Dual 10A 0 6V 3 6V Adj Switching Regulator VCCINT 1 00V 40 PTD08D210W VoutB Dual 10A 0 6V 3 6V Adj Switching Regulator VCCPINT 1 00V 40 PTD08D210W VoutA U18 Dual 10A...

Page 58: ...able at TI page www ti com fusiondocs Monitoring Voltage and Current Voltage and current monitoring and control are available for selected power rails through Texas Instruments Fusion Digital Power gr...

Page 59: ...3 Rail 3 VCCAUX 1 8 1 62 1 53 0 5 5 1 2 07 10 41 90 4 Rail 4 VCCPAUX 1 8 1 62 1 53 0 5 5 1 2 07 10 41 90 Notes 1 The values defined in these columns are the voltage current and temperature thresholds...

Page 60: ...og to Digital Converter User Guide for details on the capabilities of the analog front end Figure 1 31 shows the XADC block diagram Table 1 33 Power Rail Specifications for UCD9248 PMBus Controller at...

Page 61: ...provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines Figure 1 32 shows the XA...

Page 62: ...nel for the XADC XADC_VAUX0P N 3 6 Auxiliary analog input channel 0 Also supports use as I O inputs when anti alias capacitor is not present XADC_VAUX8N P 7 8 Auxiliary analog input channel 8 Also sup...

Page 63: ...tions are listed in Table A 2 Table A 1 Default Switch Settings Switch Position Setting Figure 1 2 Callout SW10 JTAG chain input select two position DIP switch 1 Off 23 2 On SW12 two position DIP swit...

Page 64: ...USB_RESET_B OFF J53 CAN BUS COMMON MODE CANL HDR 1 2 J56 JTAG HDR J58 PIN 2 3 3V SEL OFF J65 XADC_VCC5V0 VCC5V0 ON HDR_1 X 3 J20 MIO3 QSPI_IO1 OFF J21 MIO2 QSPI_IO0 OFF J22 MIO4 QSPI_IO2 OFF J25 MIO5...

Page 65: ...3_P LA13_N GND LA17_P_CC LA17_N_CC GND LA23_P LA23_N GND LA26_P LA26_N GND TCK TDI TDO 3P3VAUX TMS TRST_L GA1 3P3V GND 3P3V GND 3P3V GND CLK1_M2C_P CLK1_M2C_N GND GND LA00_P_CC LA00_N_CC GND LA03_P LA...

Page 66: ...t version Always refer to the ZC702 Evaluation Kit product page www xilinx com products boards and kits EK Z7 ZC702 G htm for the latest FPGA pins constraints file ZC702 Board UCF Listing NET FPGA_DON...

Page 67: ...ANDARD LVCMOS25 Bank 13 VCCO VADJ IO_L17P_T2_13 NET FMC2_LPC_LA30_N LOC AB6 IOSTANDARD LVCMOS25 Bank 13 VCCO VADJ IO_L17N_T2_13 NET FMC2_LPC_LA32_P LOC Y4 IOSTANDARD LVCMOS25 Bank 13 VCCO VADJ IO_L18P...

Page 68: ...C K15 IOSTANDARD LVCMOS25 Bank 34 VCCO VADJ IO_L1N_T0_34 NET FMC1_LPC_LA14_P LOC J16 IOSTANDARD LVCMOS25 Bank 34 VCCO VADJ IO_L2P_T0_34 NET FMC1_LPC_LA14_N LOC J17 IOSTANDARD LVCMOS25 Bank 34 VCCO VAD...

Page 69: ...D LVCMOS25 Bank 35 VCCO VADJ IO_L10P_T1_AD11P_35 NET FMC1_LPC_LA33_N LOC A19 IOSTANDARD LVCMOS25 Bank 35 VCCO VADJ IO_L10N_T1_AD11N_35 NET FMC1_LPC_LA27_P LOC C17 IOSTANDARD LVCMOS25 Bank 35 VCCO VADJ...

Page 70: ...1 PS_MIO41_501 NET SDIO_DAT1_LS LOC B11 Bank 501 PS_MIO43_501 NET SDIO_CD_DAT3_LS LOC B9 Bank 501 PS_MIO45_501 NET CAN_TXD_LS LOC B10 Bank 501 PS_MIO47_501 NET USB_UART_TX LOC C14 Bank 501 PS_MIO49_50...

Page 71: ...2 LOC M6 Bank 502 PS_DDR_BA2_502 NET PS_DDR3_BA1 LOC L6 Bank 502 PS_DDR_BA1_502 1 5v NET PS_DDR3_BA0 LOC L7 Bank 502 PS_DDR_BA0_502 NET PS_DDR3_ODT LOC P5 Bank 502 PS_DDR_ODT_502 NET PS_DDR3_CS_B LOC...

Page 72: ...850 v1 2 April 4 2013 Appendix D Board Specifications Dimensions Width 7 750 in 19 685 cm Length 7 150 in 18 161 cm Environmental Temperature Operating 0 C to 45 C Storage 25 C to 60 C Humidity 10 to...

Page 73: ...any terms htm Solution Centers See the Xilinx Solution Centers for support on devices software tools and intellectual property at all stages of the design cycle Topics include design assistance adviso...

Page 74: ...r Guide UG480 7 Series FPGAs XADC Dual 12 Bit 1MSPS Analog to Digital Converter User Guide UG585 Zynq 7000 All Programmable SoC Technical Reference Manual UG586 7 Series FPGAs Memory Interface Solutio...

Page 75: ...1 1413485 PDF RTC 8564JE 10 Digilent www digilentinc com and www digilentinc com Products Catalog cfm NavPath 2 401 Cat 9 Pmod Peripheral Modules 11 NXP Semiconductors ics nxp com TJA01040 12 Texas I...

Page 76: ...onformity To view the Declaration of Conformity online visit www xilinx com support documentation boards_and_kits ce declarations of conformit y xtp251 zip Directives 2006 95 EC Low Voltage Directive...

Page 77: ...eral requirements EN 60950 1 2006 Information technology equipment Safety Part 1 General requirements Markings This product complies with Directive 2002 96 EC on waste electrical and electronic equipm...

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