ZC702 Board User Guide
www.xilinx.com
29
UG850 (v1.2) April 4, 2013
Feature Descriptions
•
LVDS Differential Output
The user clock circuit is shown in
Figure 1-12
.
The Silicon Labs Si570 data sheet is available on the Silicon Labs website
[Ref 6]
.
Processing System Clock Source
[
Figure 1-2
, callout
8
]
The Processing System (PS) clock source is a 1.8V LVCMOS single-ended fixed
33.33333 MHz oscillator at U65. It is wired to PS bank 500, pin F7 (PS_CLK), on the XC7Z020
AP SoC.
•
Oscillator: SiTime SiT8103AC-23-18E-33.33333 (33.3 MHz)
•
Frequency jitter: 50 ppm
•
Single-ended output
For more details, see the SiTime SiT8103 data sheet
[Ref 5]
.
The system clock circuit is shown in
Figure 1-13
.
X-Ref Target - Figure 1-12
Figure 1-12:
User Clock Source
UG850_c1_12_030513
GND
VCC3V3
1
2
3
8
7
6
U28
R20
4.7K
Ω
5%
C216
0.01
µ
F 25V
X7R
4
5
GND
VCC3V3
Si570
Programmable
Oscillator
NC
OE
GND
SCL
SDA
VDD
CLK-
CLK+
R417
100
Ω
1%
USRCLK SDA
USR CLK SCL
USRCLK N
USRCLK P
