ZC702 Board User Guide
www.xilinx.com
47
UG850 (v1.2) April 4, 2013
Feature Descriptions
Table 1-26
lists the user pushbutton connections to XC7Z020 AP SoC U1.
User PMOD GPIO Headers
[
Figure 1-2
, callout
28
]
The ZC702 board supports two GPIO headers J62 and J63. The PMOD nets connected to
these headers are dual-purpose, with the
User LEDs, page 43
wired in parallel to the header
pins.
J63 has a second dual-purpose function. The even numbered pins are wired in parallel to
the ARM PJTAG header J41 pins TDI, TIMS, TCK, and TDO. The J41 PJTAG signals are
connected to AP SoC Bank 13 GPIO pins which simultaneously drive J41 and J63. When J41
is used for ARM PJTAG functionality, the J63 even numbered pin should not be used. When
J63 even numbered pins are used as GPIO, connector J41 should not be used.
Figure 1-25
shows the user GPIO male pin header circuits.
X-Ref Target - Figure 1-24
Figure 1-24:
User PS Pushbutton and DIP Switch Circuit
Table 1-26:
User PS Switch Connections to XC7Z020 AP SoC U1
XC7Z020 AP SoC (U1) Pin
Net Name
Switch and Pin Reference
B6
PS_DIP_SW0
SW13.4 and SW15.1
C5
PS_DIP_SW1
SW14.4 and SW15.2
VCCMIO_PS (1.8V)
R413
4.7 k
Ω
0.1 W
5%
GND
4
3
2
1
SW13
UG850_c1_24_030513
VCCMIO_PS (1.8V)
R414
4.7 k
Ω
0.1 W
5%
GND
4
3
2
1
SW14
PS_DIP_SW0
PS_DIP_SW1
1
2
4
VCCMIO_PS (1.8V)
3
SW15
SDA02H1SBD
