ZC702 Board User Guide
www.xilinx.com
28
UG850 (v1.2) April 4, 2013
Feature Descriptions
System Clock
[
Figure 1-2
, callout
7
]
The system clock source is an LVDS 200 MHz oscillator at U43. It is wired to a multi-region
clock capable (MRCC) input on programmable logic (PL) bank 35. The signal pair is named
SYSCLK_P and SYSCLK_N and each signal is connected to U1 pins D18 and C19 respectively
on the XC7Z020 AP SoC.
•
Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)
•
Frequency jitter: 50 ppm
•
Differential Output
For more details, see the SiTime SiT9102 data sheet
[Ref 5]
. The system clock circuit is
shown in
Figure 1-11
.
Programmable User Clock
[
Figure 1-2
, callout
8
]
The ZC702 board has a programmable low-jitter 3.3V LVDS differential oscillator (U28)
connected to the MRCC inputs of bank 13. This USRCLK_P and USRCLK_N clock signal pair
is connected to XC7Z020 AP SoC U1 pins Y9 and Y8 respectively. On power-up the user
clock defaults to an output frequency of 156.250 MHz. User applications can change the
output frequency within the range of 10 MHz to 810 MHz through an I
2
C interface. Power
cycling the ZC702 board reverts the user clock to the default frequency of 156.250 MHz.
•
Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz–810 MHz)
U28.4
USRCLK_P
Y9
J65.3
PS_CLK
F7 (Bank 500)
X-Ref Target - Figure 1-11
Figure 1-11:
System Clock Source
Table 1-12:
Clock Connections, Source to XC7Z020 AP SoC
Clock Source Pin
Net Name
XC7Z020 (U1) Pin
UG850_c1_11_030513
GND
VCC2V5
SIT9102
200 MHz
Oscillator
OE
NC
GND
VCC
OUT_B
OUT
1
2
3
6
5
4
U43
R168
100
Ω
1%
SYSCLK_P
SYSCLK_N
C71
0.1
µ
F 10V
X5R
