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Xilinx Virtex-4 RocketIO User Manual Download Page 125

Embedded Tri-Mode Ethernet MAC User Guide

www.xilinx.com

125

UG074 (v2.2) February 22, 2010

10/100/1000 Serial Gigabit Media Independent Interface (SGMII)

R

MGT Elastic Buffer (Ring Buffer)

The RX ring buffer in the MGTs has 64 entries, and acts as an elastic buffer. Upon 
initialization or reset, the buffer goes to half full. However, the buffer cannot be assumed to 
be exactly half full at the start of frame reception. Additionally, the underflow and 
overflow thresholds are not exact.

Figure 4-18

 illustrates the elastic buffer depths and thresholds of MGTs in Virtex-4 devices. 

Each FIFO word corresponds to a single character of data (equivalent to a single byte of 
data following 8B/10B decoding).

The shaded area represents the usable buffer for the duration of frame reception.

•

If the buffer is filling during frame reception, then there are 57 – 34 = 23 FIFO 
locations available before the buffer hits the overflow mark.

•

If the buffer is emptying during reception, then there are 30 – 16 = 14 FIFO locations 
available before the buffer hits the underflow mark.

This analysis assumes that the buffer is approximately at the half-full level at the start of 
the frame reception. There are, as illustrated, two locations of uncertainty above and below 
the exact half-full mark of 32. The uncertainty is a result of the clock correction decision, 
which is performed in a different clock domain.

Since there is a worst case scenario of one clock edge difference every 5000 clock periods, 
the maximum number of clock cycles (bytes) that can exist in a single frame passing 
through the buffer before an error occurs is 5,000 x 14 = 70,000 bytes.

Table 4-4

 translates this into maximum frame lengths at different Ethernet MAC speeds. 

The situation is worse at SGMII speeds lower than 1 Gb/s because bytes are repeated 
multiple times.

Figure 4-18:

Elastic Buffer Size for MGTs

Table 4-4:

Maximum Frame Sizes for MGT RX Elastic Buffers (100 ppm Clock Tol.)

Standard

Speed

Maximum Frame Size

1000BASE-X

1 Gb/s only

70,000

SGMII

1 Gb/s

70,000

64

57 - Overflow M

a

rk

34

30

16 - Underflow M

a

rk

GT11 RX El

as

tic B

u

ffer

UG074_c6_28_012408

www.BDTIC.com/XILINX

Summary of Contents for Virtex-4 RocketIO

Page 1: ...R Virtex 4 FPGA Embedded Tri Mode Ethernet MAC User Guide UG074 v2 2 February 22 2010 www BDTIC com XILINX ...

Page 2: ...r to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF ...

Page 3: ...age 78 through Table 3 31 page 83 Added Connecting the MDIO to an External PHY and Figure 3 49 page 96 Revised Ethernet MAC I Os in Figure 3 55 page 97 Figure 3 60 page 103 Figure 3 65 page 112 Figure 3 71 page 120 and Figure 3 75 page 128 Revised Figure 3 66 page 113 Added information to Auto Negotiation Interrupt page 145 Added information to SGMII Standard page 146 In Chapter 4 Revised sample c...

Page 4: ... X PCS PMA 8 bit Data Client Clock Management page 126 Added IDELAY component to Figure 3 61 Figure 3 62 Figure 3 63 and Figure 3 64 Revised the GT11 block in Figure 3 72 and Figure 3 73 Modified text in 10 100 1000 SGMII Clock Management page 121 8 Bit Data Client page 129 and 16 Bit Data Client page 130 In Chapter 6 Use Models Replaced Interfacing to an FPGA Fabric Based Statistics Block page 15...

Page 5: ...hown in Figure 4 27 Section 1000BASE X PCS PMA Clock Management in Chapter 4 The external high quality reference clock for the 16 bit Data Client MGT changed from 125 MHz to 250 MHz The GT11 clock schemes are simplified as shown in Figure 4 28 Table 4 13 Corrected 4 8 7 Pause 10 and 11 reversed Section MGT Elastic Buffer Ring Buffer in Chapter 4 Corrected underflow overflow marks and as a result c...

Page 6: ...8 7 in Table 4 14 page 144 values 01 and 10 were switched Rewrote item number 1 for 1000BASE X auto negotiation summary Overview of Operation page 151 Updated the link in the first bullet of Global Buffer Usage page 165 05 12 09 2 0 Chapter 4 In sections 1 Gb s GMII Only page 107 Tri Mode Operation page 109 Tri Mode Operation with Byte PHY Enabled Full Duplex Only page 110 1 Gb s RGMII Clock Manag...

Page 7: ...stment page 46 and Flow Control Block page 61 with the full duplex mode requirement 02 22 10 2 2 Chapter 4 Replaced EMAC CLIENTTXGMIIMIICLKOUT with GTX_CLK in Tri Mode Operation page 109 Updated BUFGMUX and GTX_CLK in upper portion of Figure 4 9 page 110 Updated description of Link Status and added table note to Table 4 11 page 141 Appendix A Changed TxMACWL to Clock Low and TxMACWH to Clock High ...

Page 8: ...Embedded Tri Mode Ethernet MAC User Guide www xilinx com UG074 v2 2 February 22 2010 www BDTIC com XILINX ...

Page 9: ...ie Off Pins 28 Management Data Input Output MDIO Interface Signals 32 Mode Dependent Signals 32 RocketIO Multi Gigabit Transceiver Signals 34 Chapter 3 Client Host and MDIO Interfaces Client Interface 37 Transmit TX Client 8 bit Wide Interface 40 Transmit TX Client 16 bit Wide Interface 47 Receive RX Client 8 bit Wide Interface 51 Receive RX Client 16 bit Wide Interface 56 Address Filtering 58 Flo...

Page 10: ...20 RGMII Signals 122 10 100 1000 Serial Gigabit Media Independent Interface SGMII 123 SGMII RX Elastic Buffer 123 10 100 1000 SGMII Interface 130 10 100 1000 SGMII Clock Management 131 SGMII Signals 132 Management Registers 134 1000BASE X PCS PMA 135 1000BASE X PCS PMA Interface 135 Shim 137 1000BASE X PCS PMA Clock Management 137 PCS PMA Signals 140 Management Registers 140 Chapter 5 Miscellaneou...

Page 11: ...t MAC Is Implemented with the DCR Bus 163 Chapter 7 Using the Embedded Ethernet MAC Accessing the Ethernet MAC from the CORE Generator tool 167 Simulating the Ethernet MAC using the Ethernet MAC wrappers 167 Appendix A Ethernet MAC Timing Model Timing Parameters 169 Input Setup Hold Times Relative to Clock 169 Clock to Output Delays 170 Core Latency 170 Timing Diagram and Timing Parameter Tables 1...

Page 12: ...12 www xilinx com Embedded Tri Mode Ethernet MAC User Guide UG074 v2 2 February 22 2010 R www BDTIC com XILINX ...

Page 13: ... design information for the client host and MDIO interfaces Chapter 4 Physical Interface describes design considerations for the supported interfaces when using the Ethernet MAC Chapter 5 Miscellaneous Functions provides useful information for designing with the Ethernet MAC Chapter 6 Use Models describes some available models and how to interface the Ethernet MAC to a processor DCR or an FPGA sta...

Page 14: ... and b means bit 8B word 64b word EXCEPTIONS 8B 10B 8 bit 10 bit 64B 66B 64 bit 66 bit Hex and binary notation Hex and binary numbers are in a monospace typeface The 0x prefix is often used to designate a hex string 0 or 1 binary 11010011 binary 0x0123456789ABCDEF Vertical ellipsis Repetitive material that has been omitted IOB 1 Name QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetitive material th...

Page 15: ...Ethernet MAC has two Ethernet MACs sharing a single host interface Either or both of the Ethernet MACs can be selected to access the Ethernet MAC registers Figure 1 1 Virtex 4 FPGA Embedded Tri Mode Ethernet MAC PPC405 Processor DS PLB Port Processor Block ISOCM ISPLB DSPLB DSOCM Control ISOCM Control DSOCM IS PLB Port Reset and Control APU APU Control DCR Generic Host Bus Host Interface Test EMAC...

Page 16: ...on transmits and stripping on receives Configured and monitored through a host interface Hardware selectable Device Control Register DCR bus or generic host bus interface Configurable flow control through Ethernet MAC Control PAUSE frames symmetrically or asymmetrically enabled Configurable support for jumbo frames of any length Configurable receive address filter for unicast multicast and broadca...

Page 17: ... interface A 1000BASE X PCS PMA sublayer when used in conjunction with the Virtex 4 FPGA RocketIO Multi Gigabit Transceiver MGT provides a complete on chip 1000BASE X implementation Figure 2 1 shows a block diagram of the Ethernet MAC block The block contains two Ethernet MACs sharing a single host interface The host interface can use either the generic host bus or the DCR bus through the DCR brid...

Page 18: ...he Ethernet MAC The Management Data I O interface MDIO allows access to the control and status registers in the external physical interface or in the PCS sublayer when configured in 1000BASE X and SGMII modes The clock management module automatically configures the output clocks to the correct frequency based on the internal speed of the Ethernet MAC 10 Mb s 100 Mb s or 1000 Mb s and the Ethernet ...

Page 19: ...gement Transmit Engine Flow Control Receive Engine Statistics Host Interface Generic Host Bus DCR Bus TX RX MDIO Interface to External PHY MDIO Interface Address Filter Registers MGT MII GMII RGMII Interface to External PHY 16 bit or 8 bit Client Interface MII GMII RGMII Interface PCS PMA Sublayer Configuration Registers UG074_2_02_081308 tx_stats_vec rx_stats_vec www BDTIC com XILINX ...

Page 20: ...access the control and status of both Ethernet MACs See Host Interface in Chapter 3 DCR Bus Interface to the PowerPC processor through the DCR bus to access the control and status of both Ethernet MACs See Using the DCR Bus as the Host Bus in Chapter 3 Physical Interface Physical interface depending on the mode of configuration See Chapter 4 Physical Interface Multi Gigabit Transceiver Interface t...

Page 21: ...XER EMAC PHYTXCLK EMAC PHYTXD 7 0 EMAC PHYMGTTXRESET EMAC PHYPOWERDOWN PHYEMAC RXBUFSTATUS 1 0 PHYEMAC RXCHARISCOMMA PHYEMAC RXCHARISK PHYEMAC RXCHECKINGCRC PHYEMAC RXCOMMADET PHYEMAC RXDISPERR PHYEMAC RXLOSSOFSYNC 1 0 EMAC PHYTXEN EMAC PHYTXER PHYEMAC COL PHYEMAC CRS EMAC PHYENCOMMAALIGN EMAC PHYLOOPBACKMSB EMAC PHYMGTRXRESET EMAC PHYSYNCACQSTATUS EMAC PHYTXCHARDISPMODE EMAC PHYTXCHARDISPVAL EMAC...

Page 22: ...e data for transmit The data path can be configured to be either 8 or 16 bits wide Bits 7 0 are used for 8 bit width The 16 bit interface is available only in 1000BASE X PCS PMA mode See Transmit TX Client 16 bit Wide Interface in Chapter 3 CLIENTEMAC TXDVLD Input Asserted by the client to indicate a valid data input at CLIENTEMAC TXD 7 0 CLIENTEMAC TXDVLDMSW Input When the width of CLIENTEMAC TXD...

Page 23: ...See Transmitter Statistics Vector in Chapter 3 EMAC CLIENTTXSTATSBYTEVLD Output Asserted if an Ethernet MAC frame byte is transmitted including destination address to FCS This is valid on every TX clock cycle EMAC CLIENTTXSTATSVLD Output Asserted by the Ethernet MAC after a frame transmission to indicate a valid EMAC CLIENTTXSTATS output See Transmitter Statistics Vector in Chapter 3 EMAC CLIENTTX...

Page 24: ...DFRAME Output This signal is asserted after the last receipt of data to indicate the reception of a non compliant frame EMAC CLIENTRXSTATS 6 0 Output The statistics data on the last received data frame The 27 bit raw RX statistics vector is multiplexed into a seven bits per RX clock cycle output for statistics gathering See Receiver Statistics Vector in Chapter 3 EMAC CLIENTRXSTATSBYTEVLD Output A...

Page 25: ...k for transmit client generated by the clock generator of the Ethernet MAC CLIENTEMAC RXCLIENTCLKIN Input Clock from receive client for the running of the receiver engine of the Ethernet MAC 1 CLIENTEMAC TXCLIENTCLKIN Input Clock from transmit client for the running of the transmitter engine of the Ethernet MAC 1 EMAC CLIENTTXGMIIMIICLKOUT Output Clock for MII GMII and RGMII modules Generated by t...

Page 26: ... read from register HOSTMIIMSEL Input When asserted the MDIO interface is accessed When deasserted the Ethernet MAC internal configuration registers are accessed HOSTREQ Input Used to signal a transaction on the MDIO interface HOSTEMAC1SEL Input This signal is asserted when EMAC1 is being accessed through the host interface and deasserted when EMAC0 is being accessed through the host interface It ...

Page 27: ...r DCR bus access When using the host bus interface the signal is connected to the logic ground EMACDCRDBUS 0 31 Output DCR read data bus EMACDCRACK Output DCR acknowledge DCRHOSTDONEIR 1 Output Interrupt signal to the PowerPC processor when the Ethernet MAC register access is done Notes 1 All the DCR bus signals are internally connected to the PowerPC processor except for the DCREMACENABLE and DCR...

Page 28: ...ed to be used dynamically to change register contents or read status registers The mode configuration vectors preconfigure the internal control registers 16 bit PCS PMA Host SGMII RGMII and MDIO interfaces but are not dynamically reconfigurable Table 2 9 Physical Interface Configuration Pins Signal Direction Description TIEEMAC CONFIGVEC 79 Input Reserved set to 1 TIEEMAC CONFIGVEC 78 74 Only used...

Page 29: ...0 68 Defines the physical interface of the Ethernet MAC These pins are mutually exclusive 10 100 MII and GMII modes are enabled when TIEEMAC CONFIGVEC 70 68 are deasserted the RGMII SGMII and 1000BASE X modes are not set TIEEMAC CONFIGVEC 70 Input RGMII mode enable Asserting this pin sets the Ethernet MAC in RGMII mode TIEEMAC CONFIGVEC 69 Input SGMII mode enable Asserting this pin sets the Ethern...

Page 30: ...thernet MAC transmitter is held in reset This signal is an input to the reset circuit for the transmitter block TIEEMAC CONFIGVEC 59 Input Transmitter Jumbo Frame Enable When this bit is 1 the Ethernet MAC transmitter allows frames larger than the maximum legal frame length specified in IEEE Std 802 3 2002 to be sent When this bit is 0 the Ethernet MAC transmitter only allows frames up to the lega...

Page 31: ...this bit is 1 the receiver block is operational When this bit is 0 the block ignores activity on the physical interface RX port TIEEMAC CONFIGVEC 49 Input Receiver VLAN Enable When this bit is 1 VLAN tagged frames are accepted by the receiver TIEEMAC CONFIGVEC 48 Input Receiver Half Duplex When this bit is 1 the receiver operates in half duplex mode When this bit is 0 the receiver operates in full...

Page 32: ...MAC UNICASTADDR 47 0 Input This 48 bit wide tie off is used to set the Ethernet MAC unicast address used by the address filter block to see if the incoming frame is destined for the Ethernet MAC The address is ordered for the least significant byte in the register to have the first byte transmitted or received for example an Ethernet MAC address of 06 05 04 03 02 01 is stored in byte 47 0 as 0x010...

Page 33: ... RGMII EMAC PHYTXEN Output 10 100 MII The data enable control signal to the PHY GMII RGMII The RGMII_TX_CTL_RISING signal to the PHY EMAC PHYTXER Output 10 100 MII The error control signal to the PHY GMII RGMII The RGMII_TX_CTL_FALLING signal to the PHY EMAC PHYTXD 7 0 Output 10 100 MII EMAC PHYTXD 3 0 is the transmit data signal to the PHY EMAC PHYTXD 7 4 are driven Low GMII The transmit data sig...

Page 34: ... The received data signal to the PHY RGMII PHYEMAC RXD 3 0 is the RGMII_RXD_RISING and PHYEMAC RXD 7 4 is the RGMII_RXD_FALLING signal from the PHY SGMII The RX_DATA from the MGT 1000BASE X PHYEMAC COL Input 10 100 MII The collision control signal from the PHY used in half duplex mode SGMII The TXRUNDISP signal from the MGT 1000BASE X PHYEMAC CRS Input 10 100 MII The carrier sense control signal f...

Page 35: ...ved tied to GND PHYEMAC RXBUFERR Input Reserved tied to GND PHYEMAC RXCOMMADET Input Reserved tied to GND PHYEMAC RXDISPERR Input Disparity error in RXDATA PHYEMAC RXLOSSOFSYNC 1 0 Input Reserved tied to GND PHYEMAC RXNOTINTABLE Input Indicates non existent 8B 10 code PHYEMAC RXRUNDISP Input Running disparity in the received serial data When RXNOTINTABLE is asserted in RXDATA this signal becomes t...

Page 36: ...36 www xilinx com Embedded Tri Mode Ethernet MAC User Guide UG074 v2 2 February 22 2010 Chapter 2 Ethernet MAC Architecture R www BDTIC com XILINX ...

Page 37: ...igned for maximum flexibility for matching the client switching fabric or network processor interface Both the transmit and receive data pathway can be configured to be either 8 bits wide or 16 bits wide with each pathway synchronous to the CLIENTEMAC TXCLIENTCLKIN transmit or CLIENTEMAC RXCLIENTCLKIN receive for completely independent full duplex operation Figure 3 1 shows a block diagram of the ...

Page 38: ... Internal Signal TX_RETRANSMIT Internal Signal Ethernet MAC Block CLIENTEMAC TXDVLD CLIENTEMAC TXD 15 0 CLIENTEMAC TXDVLDMSW PHY CLIENT PHYEMAC GTXCLK TIEEMAC CONFIGVEC 66 CLIENTEMAC TXCLIENTCLKIN PHYEMAC MIITXCLK TX_ACK Internal signal TX_ACK_EARLY Internal Signal TX_UNDERRUN Internal Signal TX_IFG_DELAY 7 0 Internal Signal EMAC CLIENTTXACK EMAC CLIENTTXRETRANSMIT EMAC CLIENTTXCOLLISION CLIENTEMA...

Page 39: ... Signal RX_GOOD_FRAME Internal Signal RX_BAD_FRAME Internal Signal Ethernet MAC Block EMAC CLIENTRXDVLD EMAC CLIENTRXD 15 0 EMAC CLIENTRXDVLDMSW PHYEMAC RXCLK CLIENTEMAC RXCLIENTCLKIN CLIENT PHY FPGA Fabric EMAC CLIENTRXGOODFRAME EMAC CLIENTRXBADFRAME CLIENTEMAC RXCLIENTCLKIN TIEEMAC CONFIGVEC 65 ug074_3_04_070105 Table 3 1 Abbreviations Used in this Chapter Abbreviation Definition Length DA Desti...

Page 40: ...n end of frame to the Ethernet MAC In SGMII or 1000BASE X PCS PMA mode the PCS engine inserts code characters in the data stream from CLIENTEMAC TXD Table 3 1 describes these code characters and IEEE Std 802 3 Clause 36 has further definitions The encapsulated data stream then appears on EMAC PHYTXD and goes to the MGT Along with EMAC PHYTXCHARISK and EMAC PHYTXCHARDISPMODE the MGT encodes the inc...

Page 41: ... the minimum frame length see Client Supplied FCS Passing page 41 Client Supplied FCS Passing In the transmission timing case shown in Figure 3 4 an Ethernet MAC is configured to have the FCS field passed in by the client see Configuration Registers page 74 The client must ensure that the frame meets the Ethernet minimum frame length requirements the Ethernet MAC does not pad the payload Figure 3 ...

Page 42: ...rent frame to signal corruption It then falls back to idle transmission EMAC PHYTXER is asserted some cycles after The client must requeue the aborted frame for transmission When an underrun occurs to request a new transmission reassert CLIENTEMAC TXDVLD on the clock cycle after the CLIENTEMAC TXUNDERRUN is asserted Figure 3 5 Frame Transmission with Underrun ug074_3_07_072705 CLIENTEMAC TXCLIENTC...

Page 43: ...dress of the second frame is awaiting transmission on CLIENTEMAC TXD When the Ethernet MAC is ready to accept data EMAC CLIENTTXACK is asserted and the transmission continues in the same manner as the single frame case The Ethernet MAC defers the assertion of EMAC CLIENTTXACK to comply with inter packet gap requirements and flow control requests Figure 3 6 Back to Back Frame Transmission ug074_3_0...

Page 44: ...es VLAN tagged frames can be extended to 1522 bytes When jumbo frame handling is disabled and the client attempts to transmit a frame that exceeds the maximum legal length the Ethernet MAC inserts an error code to corrupt the current frame and the frame is truncated to the maximum legal length When jumbo frame handling is enabled frames longer than the legal maximum are transmitted error free For ...

Page 45: ... the transfer and CLIENTEMAC TXDVLD is deasserted to 0 If the EMAC CLIENTTXRETRANSMIT signal is 1 in the same clock cycle as the EMAC CLIENTTXCOLLISION signal is 1 the client must resubmit the previous frame to the Ethernet MAC for retransmission CLIENTEMAC TXDVLD must be asserted to the Ethernet MAC within eight clock cycles of the EMAC CLIENTTXCOLLISION signal to meet Ethernet timing requirement...

Page 46: ...Configuration Registers page 74 then the Ethernet MAC exerts back pressure to delay the transmission of the next frame until the requested number of idle cycles has elapsed The number of idle cycles is controlled by the value on the CLIENTEMAC TXIFGDELAY port at the start of frame transmission Figure 3 10 shows the Ethernet MAC operating in this mode In full duplex configurations the minimum IFG i...

Page 47: ...y two as shown in Figure 3 1 page 38 Using a DCM with the transmit client clock EMACCLIENT TXCLIENTCLKOUT as an input the divide by two clock signal is generated See Figure 4 28 page 139 for more information As in the 8 bit client interface the PCS engine inserts code characters in the data stream from CLIENTEMAC TXD Table 3 1 describes these code characters and IEEE Std 802 3 Clause 36 has furthe...

Page 48: ...yte Case CLIENTEMAC TXCLIENTCLKIN PHYEMAC MIITXCLK CLIENTEMAC TXCLIENTCLKIN 2 CLIENTEMAC TXD 15 0 CLIENTEMAC TXDVLD EMAC CLIENTTXACK CLIENTEMAC TXUNDERRUN DA SA DATA EMAC CLIENTTXCOLLISION EMAC CLIENTTXRETRANSMIT CLIENTEMAC TXDVLDMSW CLIENTEMAC TXFIRSTBYTE ug074_3_13_080705 EMAC PHYTXCHARISK SGMII or 1000BASE X PCS PMA only EMAC PHYTXCHARDISPMODE SGMII or 1000BASE X PCS PMA only EMAC PHYTXD 7 0 SG...

Page 49: ...ITXCLK clock cycle both CLIENTEMAC TXDLVD and CLIENTEMAC TXDVLDMSW must be set High to indicate that the first two bytes of the destination address of the second frame is ready for transmission on CLIENTEMAC TXD 15 0 In 16 bit mode this one PHYEMAC MIITXCLK clock cycle IFG corresponds to a 2 byte gap versus a 1 byte gap in 8 bit mode between frames in the back to back transfer Figure 3 12 16 Bit T...

Page 50: ...MIITXCLK CLIENTEMAC TXCLIENTCLKIN 2 CLIENTEMAC TXD 15 0 D n 2 D n 3 D n D n 1 DA1 DA0 DA3 DA2 DA5 DA4 CLIENTEMAC TXDVLD CLIENTEMAC TXDVLDMSW EMAC CLIENTTXACK CLIENTEMAC TXFIRSTBYTE CLIENTEMAC TXUNDERRUN EMAC CLIENTTXCOLLISION EMAC CLIENTTXRETRANSMIT 1st Frame IFG 2nd Frame ug074_3_15_101004 CLIENTEMAC TXCLIENTCLKIN PHYEMAC MIITXCLK CLIENTEMAC TXCLIENTCLKIN 2 CLIENTEMAC TXD 15 0 D n 1 D n 2 DA1 DA0...

Page 51: ...he client in the data payload an exception is when FCS passing is enabled See Client Supplied FCS Passing page 54 Therefore when client supplied FCS passing is disabled EMAC CLIENTRXDVLD 0 between frames for the duration of the padding field if present the FCS field carrier extension if present the IFG following the frame and the preamble field of the next frame When client supplied FCS passing is...

Page 52: ...ng of a normal inbound frame transfer in SGMII and 1000BASE X PCS PMA mode Figure 3 16 Inbound Frame Transfer Front CLIENTEMAC RXCLIENTCLKIN PRE PREAMBLE TL DA SA Data I1 I2 I2 I2 I2 S PHYEMAC RXCHARISCOMMA PHYEMAC RXCHARISK PHYEMAC RXD 7 0 EMAC CLIENTRXD 7 0 EMAC RXCLIENTDVLD EMAC CLIENTRXGOODFRAME EMAC CLIENTRXBADFRAME EMAC CLIENTRXSTATS 6 0 EMAC CLIENTRXSTATSVLD UG074_3_18_072705 Figure 3 17 In...

Page 53: ... in SGMII and 1000BASE X PCS PMA modes The following conditions cause the assertion of EMAC CLIENTRXBADFRAME Standard Conditions FCS errors occur Packets are shorter than 64 bytes undersize or fragment frames Figure 3 18 Frame Reception with Error DA SA DATA L T ug074_3_20_080805 EMAC CLIENTRXD 7 0 EMAC CLIENTRXGOODFRAME EMAC CLIENTRXBADFRAME CLIENTEMAC RXCLIENTCLKIN EMAC CLIENTRXDVLD Figure 3 19 ...

Page 54: ...n error code is received in the 1 Gb frame extension field A valid pause frame addressed to the Ethernet MAC is received when flow control is enabled Refer to Flow Control Block page 61 for more information 1000BASE X SGMII Specific Conditions When in 1000BASE X or SGMII mode these errors can also cause a frame to be marked as bad Unrecognized 8B 10B code group received during the packet 8B 10B ru...

Page 55: ... can be extended to 1522 bytes When jumbo frame handling is disabled and the Ethernet MAC receives a frame exceeding the maximum legal length EMAC CLIENTRXBADFRAME is asserted When jumbo frame handling is enabled frames longer than the legal maximum are received in the same way as shorter frames For more information on enabling and disabling jumbo frame handling see Configuration Registers page 74...

Page 56: ...the padding bytes from the frame Disabled When the Length Type error checking is disabled see Receiver Configuration Register Word 1 page 75 the Length Type error checks described above are not performed A frame containing only these errors causes EMAC CLIENTRXGOODFRAME to be asserted Disabling this check does not disable total frame length checks Any frame of less than 64 total bytes minimum fram...

Page 57: ... data valid signals are shown in the even byte case Figure 3 22 In the odd byte case Figure 3 23 EMAC CLIENTRXDVLDMSW is deasserted one clock cycle earlier compared to the EMAC CLIENTRXDVLD signal after the reception of the frame EMAC CLIENTRXD 7 0 contains the data in this odd byte case Figure 3 22 16 Bit Receive Even Byte Case CLIENTEMAC RXCLIENTCLKIN PHYEMAC RXCLK CLIENTEMAC RXCLIENTCLKIN 2 EMA...

Page 58: ...client interface only if they pass the filter When the AF function is disabled all incoming RX frames are passed to the client interface For system monitoring the event of a frame failing the filter is signaled Equally when a frame passes the filter a match is indicated to the client by using the output pins EMAC CLIENTRXDVLD and EMAC CLIENTRXFRAMEDROP together Table 3 2 shows the values of the tw...

Page 59: ...e interface does not initialize the four multicast address register values When the host interface is used all the address filter registers are accessible by software using either the DCR bus or the generic host bus The tie interface initialization values to the registers can be overridden by the software through the host interface Also the four multicast address registers are programmed through t...

Page 60: ...led in this timing diagram Figure 3 25 Frame Matching Timing Diagram 16 Bit Mode n n 4 n 5 n 2 n 1 n 3 n 1 n 2 n 3 n 4 n 5 n 6 CLIENTEMAC RXCLIENTCLKIN EMAC CLIENTRXDVLD EMAC CLIENTRXD 15 0 EMAC CLIENTRXGOODFRAME PHYEMAC RXCLK EMAC CLIENTRXFRAMEDROP Previous Frame Dropped Current Frame Passed DA DA1 DA0 DA3 DA2 DA5 DA4 ug074_3_27_080805 EMAC CLIENTRXDVLDMSW Figure 3 26 Frame Matching Failed Timing...

Page 61: ...figure has a reference clock slightly faster than the nominal 125 MHz The Ethernet MAC on the left side of the figure has a reference clock slightly slower than the nominal 125 MHz This results in the Ethernet MAC on the left side of the figure not being able to match the full line rate of the Ethernet MAC on the right side due to clock tolerances The left Ethernet MAC is illustrated as performing...

Page 62: ...ssion of frames for the period of time defined in the received pause control frame For example the right Ethernet MAC of Figure 3 28 ceases transmission after receiving the pause control frame transmitted by the left Ethernet MAC In a well designed system the right Ethernet MAC ceases transmission before the client FIFO of the left Ethernet MAC is overflowed This provides time to empty the FIFO to...

Page 63: ...ng the Configuration Registers The pause_time in the PAUSE frame is the value from the CLIENTEMAC PAUSEVAL 15 0 Receiving a PAUSE Control Frame When an error free frame is received by the Ethernet MAC it examines the following information The destination address field is matched against the Ethernet MAC control multicast address and the configured source address for the Ethernet MAC see Configurat...

Page 64: ...the right Ethernet MAC due to clock tolerances Over time the FIFO fills and overflows This example implements a flow control method to reduce over a long time period the full line rate of the right Ethernet MAC to less than the full line rate capability of the left Ethernet MAC Method 1 Choose a FIFO with a nearly full occupancy threshold A 7 8 occupancy is used in this description but the choice ...

Page 65: ...ls to the second threshold of 3 4 occupancy at point B triggering the zero duration pause control frame request the pause cancel command 4 Upon receiving this second pause control frame the right hand Ethernet MAC resumes transmission 5 Normal operation resumes and the FIFO occupancy again gradually increases over time At point C the flow control cycle repeats Statistics Vector Transmitter Statist...

Page 66: ...yte DA to FCS inclusive is being transmitted The signal is valid on every CLIENTEMAC TXCLIENTCLKIN cycle Figure 3 32 Transmitter Statistics Mux Timing UG074_03_34_080805 0 1 2 3 4 5 28 29 30 31 CLIENTEMAC TXCLIENTCLKIN TX_STATISTICS_VALID internal signal TX_STATISTICS_VECTOR 31 0 internal signal EMAC CLIENTTXSTATSVLD EMAC CLIENTTXSTATS Figure 3 33 Transmitter Statistics Mux Block Diagram TX_STATIS...

Page 67: ...on 31 PAUSE_FRAME_TRANSMITTED Asserted if the previous frame was a pause frame initiated by the Ethernet MAC in response to asserting CLIENTEMAC PAUSEREQ 30 Reserved Undefined 29 Reserved Returns a logic 0 28 25 TX_ATTEMPTS 3 0 The number of attempts made to transmit the previous frame A 4 bit number where 0x0 one attempt 0x1 two attempts up to 0xF which describes 16 attempts 24 Reserved Returns a...

Page 68: ...previous frame in number of bytes The count sticks at 16383 for jumbo frames larger than this value Stops at 16383 4 CONTROL_FRAME Asserted if the previous frame has the special Ethernet MAC control type code 88 08 in the LT field 3 UNDERRUN_FRAME Asserted if the previous frame contains an underrun error 2 MULTICAST_FRAME Asserted if the previous frame contains a multicast address in the destinati...

Page 69: ...ics MUX Block Diagram RX_STATISTICS_VECTOR 26 0 Internal Signal RX_STATISTICS_VALID Internal Signal Ethernet MAC RXSTATSMUX RXSTATSDEMUX User Defined Statistics Processing Block 26 0 EMAC CLIENTRXSTATSBYTEVLD EMAC CLIENTRXSTATS 6 0 CLIENTEMAC RXCLIENTCLKIN CLIENTEMAC RXCLIENTCLKIN RESET RXSTATSVEC 26 0 RXSTATSVLD EMAC CLIENTRXSTATSVLD ug074_3_38_080805 Ethernet MAC Block FPGA Fabric CLIENTEMAC RXC...

Page 70: ...ble 3 5 Bit Definitions for the Receiver Statistics Vector RX_STATISTICS_VECTOR Name Description 26 ALIGNMENT_ERROR Used in 10 100 MII mode If an odd number of nibbles is received the last nibble is ignored If the frame without this nibble has an incorrect FCS this bit is asserted If the frame has a valid FCS this bit is not asserted 25 Length Type Out of Range Asserted if the LT field contains a ...

Page 71: ...defined 21 VLAN_FRAME Asserted if the previous frame contains a VLAN identifier in the LT field when receiver VLAN operation is enabled 20 OUT_OF_BOUNDS Asserted if the previous frame exceeded the specified IEEE Std 802 3 2002 maximum legal length see Maximum Permitted Frame Length Jumbo Frames page 55 This is only valid if jumbo frames are disabled 19 CONTROL_FRAME Asserted if the previous frame ...

Page 72: ...ernet MACs share a single host interface The host interface brings the Ethernet MAC host bus from the Ethernet MAC out to the fabric The host interface unit also contains a DCR bus bridge This allows the user to access the Ethernet MAC registers through the DCR bus Figure 3 38 shows the internal structure of the host interface The EMAC1 signal is provided by the HOSTEMAC1SEL input signal when usin...

Page 73: ... is one of the methods used by the PowerPC processor to determine when the host interface completes a DCR host access command The interrupt request DCRHOSTDONEIR signal is only active when the DCR bus is used and the host interface register IRENABLE is programmed to enable interrupt This signal is active High and level sensitive When a host access through the DCR bus is completed the DCRHOSTDONEIR...

Page 74: ...ce Any time an address shown in Table 3 7 is accessed a 32 bit read or write is performed from the same configuration word with the exception of the read only Ethernet MAC mode configuration register and the RGMII SGMII configuration register Only the speed selection is both readable and writable in the Ethernet MAC mode configuration register The configuration registers and the contents of the re...

Page 75: ...s the comparison of the L T field with the size of the data TIEEMAC CONFIGVEC 63 R W 26 Half duplex mode When this bit is 1 the receiver operates in half duplex mode When the bit is 0 the receiver operates in full duplex mode TIEEMAC CONFIGVEC 48 R W 27 VLAN enable When this bit is 1 the receiver accepts VLAN tagged frames The maximum payload length increases by four bytes TIEEMAC CONFIGVEC 49 R W...

Page 76: ...he Ethernet MAC transmitter is ready for the FCS field from the client TIEEMAC CONFIGVEC 58 R W 30 Jumbo frame enable When this bit is 1 the transmitter sends frames greater than the maximum length specified in IEEE Std 802 3 2002 When this bit is 0 it only sends frames less than the specified maximum length TIEEMAC CONFIGVEC 59 R W 31 Reset When this bit is 1 the transmitter is reset The bit auto...

Page 77: ...transmit data client interface is 16 bits wide When this bit is 0 the transmit data client interface is 8 bits wide This bit is valid only when using 1000BASE X PCS PMA mode TIEEMAC CONFIGVEC 66 R 26 Host Interface enable When this bit is 1 the host interface is enabled When this bit is 0 the host interface is disabled See Tie Off Pins on page 28 TIEEMAC CONFIGVEC 67 R 27 1000BASE X mode enable Wh...

Page 78: ...II half duplex mode Valid in RGMII mode configuration only This bit is 0 for half duplex mode and 1 for full duplex mode This displays the duplex information from PHY to Ethernet MAC encoded by GMII_RX_DV and GMII_RX_ER during the IFG 0 R 3 2 RGMII speed Valid in RGMII mode configuration only Link information from PHY to Ethernet MAC as encoded by GMII_RX_DV and GMII_RX_ER during the IFG This 2 bi...

Page 79: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x340 RESERVED MDIOEN CLOCK_DIVIDE 5 0 Bit Description Default Value R W 5 0 Clock divide 5 0 This value is used to derive the EMAC PHYMCLKOUT for external devices See MDIO Interface page 93 All 0s R W 6 MDIO enable When this bit is 1 the MDIO interface is used to access the PHY When this bit is 0 the MDIO interface is ...

Page 80: ...ycles during a read operation Address Filter Registers Address Filter Register access includes the address filter registers and the multicast address table registers The Ethernet MAC has five address filter registers with access through the host interface Table 3 15 Figure 3 41 Configuration Register Read Timing HOSTCLK HOSTADDR 8 0 HOSTADDR 9 HOSTOPCODE 1 HOSTMIIMSEL HOSTRDDATA 31 0 ug074_3_43_08...

Page 81: ...lticast Address Register 3 ADDR 16 15 17 23 LSB MSB MSB LSB ADDR RNW 0x38C 0x78C ug074_3_44_080805 Table 3 16 Unicast Address Word 0 MSB LSB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x380 UNICAST_ADDRESS 31 0 Bit Description Default Value R W 31 0 Unicast Address 31 0 This address is used to match the Ethernet MAC against the destination address of any ...

Page 82: ...R W 15 0 Multicast Address 47 32 The multicast address bits 47 32 are temporarily deposited into this register for writing into a multicast address register All 0s R W 17 16 Multicast Address This 2 bit vector is used to choose the multicast address register to access 00 Multicast Address Register 0 01 Multicast Address Register 1 10 Multicast Address Register 2 11 Multicast Address Register 3 All...

Page 83: ...anslates commands carried over the DCR bus into Ethernet MAC host bus signals These signals are then input into one of the Ethernet MACs The DCR bus bridge contains four device control registers The first two are used as data registers each is 32 bits wide dataRegMSW and dataRegLSW The third is used as a control register cntlReg The fourth device control register is used as a ready status register...

Page 84: ...W 32 bits R W _ _1101 dataRegLSW 32 bits R W _ _1110 cntlReg 32 bits R W _ _1111 RDYstatus 32 bits R 1 Notes 1 This register is Read Only Table 3 22 DCR Data Register dataRegMSW DCR Offset MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xC dataRegMSW Bit Description Default Value 31 0 Data Data input from the DCR bus for the Ethernet MAC registers is ...

Page 85: ...en this bit is asserted the data in either dataRegLSW or dataRegMSW is written into an Ethernet MAC register When this bit is deasserted the operation to be performed is read 0 17 20 Reserved All 0s 21 EMAC1SEL When this bit is asserted the address code is for the EMAC1 registers Otherwise the address code is for the EMAC0 registers This bit is essentially the bit 10 of the address code 0 22 31 Ad...

Page 86: ...olds MDIO write data for output to the MDIO write data bus In the case of an MDIO read there is no need to Table 3 25 DCR Ready Status Register RDYStatus Read Only DCR Offset MSB LSB 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xF RESERVED CFG WR1 CFG RR1 AF WR1 AF RR1 MIIM WR1 MIIM RR1 STAT RR1 RSVD CFG WR0 CFG RR0 AF WR0 AF RR0 MIIM WR0 MIIM RR0 STAT RR0...

Page 87: ...F RST0 MIIM WST0 MIIM RST0 STAT RST0 Bit Description Ethernet MAC Default Value 0 16 Reserved 0 17 Configuration Write Interrupt Request bit EMAC1 0 18 Configuration Read Interrupt Request bit EMAC1 0 19 Address Filter Write Interrupt Request bit EMAC1 0 20 Address Filter Read Interrupt Request bit EMAC1 0 21 MDIO Write Interrupt Request bit EMAC1 0 22 MDIO Read Interrupt Request bit EMAC1 0 23 St...

Page 88: ...ble bit EMAC1 0 23 Statistics IP Read IR enable bit 1 EMAC1 0 24 Reserved 0 25 Configuration Write IR enable bit EMAC0 0 26 Configuration Read IR enable bit EMAC0 0 27 Address Filter Write IR enable bit EMAC0 0 28 Address Filter Read IR enable bit EMAC0 0 29 MDIO Write IR enable bit EMAC0 0 30 MDIO Read IR enable bit EMAC0 0 31 Statistics IP Read IR enable bit 1 EMAC0 0 Notes 1 For more informatio...

Page 89: ...0 register use the little endian bit numbering convention In the DCR bridge implementation there is no conversion to or from big endian to little endian The bit positions are mapped directly in a one to one correspondence big endian bit 0 is mapped directly to little endian bit 31 big endian bit 1 is mapped directly to little endian bit 30 and onward The decode of the address code also generates t...

Page 90: ...umber are then written to the DCR dataRegLSW register The mapping is shown in Figure 3 45 The DCR bridge runs at the same clock frequency as the PowerPC processor Because the host bus is not a high performance bus HOSTCLK runs at a lower frequency The HOSTCLK frequency must be an integer divide of the DCR clock frequency and the two clocks must be phase aligned The DCR bridge ignores any new DCR c...

Page 91: ...ig_eth_mac_ds200 pdf Table 3 29 Address Code Groups for DCR Host Bus Access Group Address Code Description EMAC0 0x200 0x39F EMAC0 registers Host Interface 0x3A0 0x3FF Host interface registers EMAC1 0x600 0x79F EMAC1 registers Notes 1 Any access to the host interface registers does not generate interrupts and does not change the RDYSTATUS register bits Table 3 30 Detailed Address Codes for DCR Hos...

Page 92: ...W 0x700 E1_EMACCONFIG Ethernet MAC configuration 0x700 R W 0x720 E1_RGMII_SGMII RGMII SGMII configuration 0x720 R 0x740 E1_MGMTCONFIG Management configuration 0x740 R W 0x780 E1_UNICASTADDRW0 Unicast address 31 0 0x780 R W 0x784 E1_UNICASTADDRW1 0x0000 Unicast Address 47 32 0x784 R W 0x788 E1_ADDRTABLECONFIGW0 Multicast address data 31 0 0x788 R W 0x78C E1_ADDRTABLECONFIGW1 0x00 RNW 00000 ADDR 1 0...

Page 93: ...number of MDIO Managed Device MMD slave entities Figure 3 46 illustrates a typical system All transactions read or write are initiated by the STA entity All MMD devices if addressed must respond to the transactions from the STA The two different MDIO transaction types for writes and reads are described in Write Transaction and Read Transaction These abbreviations are used in this chapter Figure 3 ...

Page 94: ...E Std 802 3 Clause 22 2 4 5 5 This address field is a 5 bit binary value capable of addressing 32 unique addresses However every MMD must respond to address 0 Therefore this address location can be used to write a single command that is obeyed by all attached MMDs such as a reset or power down command This requirement dictates that the PHYAD for any particular MMD must not be set to 0 to avoid pos...

Page 95: ...nally integrated by using an IOBUF with an appropriate I O standard for the external PHY as illustrated in Figure 3 49 To obtain this functionality whenever the host interface is used the EMAC s Management Data Input Output MDIO Interface signals are wired as shown in Figure 3 49 with TIEEMAC CONFIGVEC 73 MDIO enable tied High This example intentionally does not use the PCS PMA sublayer a GMII or ...

Page 96: ...t signals are tied to a logic level PHYEMAC MDIN must be tied High when not connected to an external PHY Alternatively the EMAC s Managements Data Input Output MDIO can be connected to a second MMD for example an external PHY device by providing the connections illustrated in Figure 3 49 Externally connected MMDs MDIO slaves must have different non zero physical addresses PHYAD from the non zero a...

Page 97: ...he MDIO clock is given by the following equation To comply with the IEEE Std 802 3 2002 specification for this interface the frequency of EMAC PHYMCLKOUT should not exceed 2 5 MHz To prevent EMAC PHYMCLKOUT from being out of specification the Clock Divide 5 0 value powers up at 000000 While this value is in the register it is impossible to enable the MDIO interface Given this even if the user has ...

Page 98: ...already has a transaction in progress The Ethernet MAC deasserts the HOSTMIIMRDY signal while the transaction across the MDIO is in progress When the transaction across the MDIO interface is completed the HOSTMIIMRDY signal is asserted by the Ethernet MAC If the transaction is a read the data is also available on the HOSTRDATA 15 0 bus As noted in Figure 3 52 if a read transaction is initiated the...

Page 99: ... files created by the CORE Generator tool will contain the clocking logic By using the CORE Generator tool the time required to instantiate the Ethernet MAC into a usable design is greatly reduced See Using the Embedded Ethernet MAC page 167 The in the following sections denotes either EMAC0 or EMAC1 Media Independent Interface MII MII is designed to IEEE Std 802 3 2002 Clause 22 It is used for 10...

Page 100: ...HOSTADDR 9 0 HOSTCLK HOSTMIIMSEL HOSTOPCODE 1 0 HOSTREQ HOSTMIIMRDY HOSTRDDATA 31 0 HOSTWRDATA 31 0 DCREMACENABLE EMACDCRACK EMACDCRDBUS 0 31 EMAC CLIENTRXSTATS 6 0 EMAC CLIENTRXSTATSBYTEVLD EMAC CLIENTRXSTATSVLD CLIENTEMAC TXD 15 0 CLIENTEMAC TXDVLD CLIENTEMAC TXDVLDMSW EMAC CLIENTTXACK EMAC CLIENTTXRETRANSMIT EMAC CLIENTTXSTATS EMAC CLIENTTXSTATSBYTEVLD EMAC CLIENTTXSTATSVLD HOSTEMAC1SEL CLIENTE...

Page 101: ...igh MII Clock Management with Clock Enable It is possible to only use two BUFGs To accomplish this BUFG reduction the client and MII logic must be constrained to run at 125 MHz Also clock enable signals must be added to the client logic Figure 4 3 shows the MII clock management with a clock enable scheme Figure 4 2 MII Clock Management CLIENTEMAC TXGMIIMIICLKIN PHYEMAC GTXCLK CLIENTEMAC TXCLIENTCL...

Page 102: ...flop clocked on the falling edge of the MII clock and routed to the client clock inputs The client logic must also be clock enabled to achieve the correct Figure 4 3 MII Clock Management with Clock Enable CLIENTEMAC TXGMIIMIICLKIN PHYEMAC GTXCLK CLIENTEMAC TXCLIENTCLKIN EMAC CLIENTTXCLIENTCLKOUT CLIENTEMAC RXCLIENTCLKIN EMAC CLIENTRXCLIENTCLKOUT PHYEMAC RXCLK EMAC PHYTXD 3 0 PHYEMAC RXD 3 0 EMAC T...

Page 103: ...e of the MII clock the data is clocked into the MAC at least 12 ns after the data is stable Using this technique the EMAC CLIENTTXACK signal must be registered at the output of the Ethernet MAC EMAC CLIENTTXACK is generated on the rising edge of the client clock input CLIENTEMAC TXCLIENTCLKIN and sampled by the client logic on the rising edge of the MII clock This technique can lead to the first b...

Page 104: ...MIIMIICLKOUT PHYEMAC RXCLK EMAC PHYTXD PHYEMAC RXD CLIENTEMAC TXCLIENTCLKIN CLIENTEMAC RXCLIENTCLKIN UG074_3_70_010906 Table 4 1 MII Interface Signals Signal Direction Description MII_TXD 3 0 _ Output Transmits data to PHY MII_TX_EN_ Output Transmits data enable to PHY MII_TX_ER_ Output Transmits error signal to PHY MII_TX_CLK_ Input Recovered transmit clock by PHY MII_CRS_ Input Carrier sense con...

Page 105: ...MII Signals Gigabit Media Independent Interface GMII is designed to IEEE Std 802 3 2002 Clause 35 It is used for 1000 Mb s The physical interface is used for tri speed operation of the Ethernet MAC GMII Interface Figure 4 6 shows the Ethernet MAC configured with GMII as the physical interface In this interface not all the ports of the Ethernet MAC are used www BDTIC com XILINX ...

Page 106: ...HOSTMIIMRDY HOSTRDDATA 31 0 HOSTWRDATA 31 0 DCREMACENABLE EMACDCRACK EMACDCRDBUS 0 31 EMAC CLIENTRXSTATS 6 0 EMAC CLIENTRXSTATSBYTEVLD EMAC CLIENTRXSTATSVLD CLIENTEMAC TXD 15 0 CLIENTEMAC TXDVLD CLIENTEMAC TXDVLDMSW EMAC CLIENTTXACK EMAC CLIENTTXRETRANSMIT EMAC CLIENTTXSTATS EMAC CLIENTTXSTATSBYTEVLD EMAC CLIENTTXSTATSVLD HOSTEMAC1SEL CLIENTEMAC PAUSEREQ CLIENTEMAC PAUSEVAL 15 0 CLIENTEMAC TXUNDER...

Page 107: ...be tied to ground The GMII_RX_CLK_ is generated from the PHY and is connected to PHYEMAC RXCLK through a DCM and a BUFG The CLIENTEMAC DCMLOCKED port must be tied High The DCM is used to shift the received GMII clock with respect to the data in order to sample a 2 ns setup 0 ns hold window at the device pads Phase shifting is applied to the DCM to fine tune the setup and i Figure 4 7 1 Gb s GMII C...

Page 108: ...MAC1CLIENTTXCLIENTCLKOUT CLIENTEMAC1RXCLIENTCLKIN EMAC1CLIENTRXCLIENTCLKOUT PHYEMAC1TXD 7 0 PHYEMAC0MIITXCLK EMAC1 TX CLIENT LOGIC RX CLIENT LOGIC OBUF GMII_TXD_1 7 0 Q D GND NC NC EMAC0CLIENTTXGMIIMIICLKOUT CLIENTEMAC0TXGMIIMIICLKIN PHYEMAC0GTXCLK CLIENTEMAC0TXCLIENTCLKIN EMAC0CLIENTTXCLIENTCLKOUT CLIENTEMAC0RXCLIENTCLKIN EMAC0CLIENTRXCLIENTCLKOUT PHYEMAC0RXCLK PHYEMAC0TXD 7 0 PHYEMAC0RXD 7 0 PHY...

Page 109: ...A DCM must be used on the GMII_RX_CLK_ clock path as illustrated in Figure 4 9 to meet the GMII input setup and hold requirements when operating at 1 Gb s Phase shifting may then be applied to the DCM to fine tune the setup and hold times of the input GMII receiver signals which are sampled at the GMII IOB input flip flops When operating at 10 Mb s and 100 Mb s the DCM is bypassed and held in rese...

Page 110: ... all external logic is clocked at 125 MHz At 100 Mb s and 10 Mb s the logic is clocked at 12 5 MHz and 1 25 MHz respectively Figure 4 9 GMII Tri Mode Operation Clock Management CLIENTEMAC TXGMIIMIICLKIN PHYEMAC GTXCLK CLIENTEMAC TXCLIENTCLKIN EMAC CLIENTTXCLIENTCLKOUT CLIENTEMAC RXCLIENTCLKIN EMAC CLIENTRXCLIENTCLKOUT CLIENTEMAC DCMLOCKED EMAC PHYTXD 7 0 EMAC BUFG BUFGMUX GTX_CLK TX CLIENT LOGIC B...

Page 111: ...TXCLK PHYEMAC RXCLK PHYEMAC RXD 3 0 PHYEMAC RXD 7 4 CLIENTEMAC DCMLOCKED CLIENTEMAC RXCLIENTCLKIN EMAC CLIENTRXCLIENTCLKOUT GTX_CLK TX Client Logic RX Client Logic OBUF ODDR D1 D2 Q Q GMII_TXD_ 3 0 GMII_RXD_ 3 0 BUFGMUX D ODDR D1 D2 Q OBUF GMII_TXD_ 7 4 IBUFG MII_TX_CLK_ SPEED_IS_10_100 SPEED_IS_10_100 I0 I1 I0 I1 BUFGMUX SPEED_IS_10_100 I0 I1 Q D Q IBUF GMII_RXD_ 7 4 D D Q1 IDDR IDDR Q2 Q1 Q2 4 b...

Page 112: ...ip flops When operating at 10 Mb s and 100 Mb s the DCM is bypassed and held in reset This is achieved using the BUFGMUX global clock multiplexer shown in Figure 4 10 It is a requirement to bypass the DCM because the clock frequency of GMII_RX_CLK_ is 2 5 MHz when operating at 10 Mb s and 2 5 MHz is below the DCM low frequency threshold for Virtex 4 FPGAs However at the 10 Mb s and 100 Mb s operat...

Page 113: ...he Hewlett Packard RGMII Specification version 1 3 and 2 0 1 Gb s RGMII Interface Figure 4 11 shows the Ethernet MAC configured with RGMII as the physical interface In this interface not all the ports of the Ethernet MAC are used GMII_COL_ Input Collision detect control signal from PHY only if tri mode is selected GMII_RX_CLK_ Input Recovered clock from data stream by PHY GMII_RXD 7 0 _ Input Rece...

Page 114: ...0 DCREMACENABLE EMACDCRACK EMACDCRDBUS 0 31 EMAC CLIENTRXSTATS 6 0 EMAC CLIENTRXSTATSBYTEVLD EMAC CLIENTRXSTATSVLD CLIENTEMAC TXD 15 0 CLIENTEMAC TXDVLD CLIENTEMAC TXDVLDMSW EMAC CLIENTTXACK EMAC CLIENTTXRETRANSMIT EMAC CLIENTTXSTATS EMAC CLIENTTXSTATSBYTEVLD EMAC CLIENTTXSTATSVLD HOSTEMAC1SEL CLIENTEMAC PAUSEREQ CLIENTEMAC PAUSEVAL 15 0 CLIENTEMAC TXUNDERRUN CLIENTEMAC TXIFGDELAY 7 0 EMAC CLIENTR...

Page 115: ...ated from the PHY and is connected to the PHYEMAC RXCLK pin and receive logic through a DCM and a BUFG A DCM must be used on the RGMII_RXC_ clock path as illustrated in Figure 4 12 to meet the RGMII 1 ns setup and 1 ns hold requirements Phase shifting may then be applied to the DCM to fine tune the setup and hold times of the input RGMII receiver signals which are sampled at the RGMII IOB input fl...

Page 116: ...een RGMII_TXC_ and the RGMII_TXD_ at the FPGA device pads This delay is specified in the Hewlett Packard RGMII Specification v2 0 to provide setup and hold time on the external interface Figure 4 13 1 Gb s RGMII Hewlett Packard v2 0 Clock Management EMAC CLIENTTXGMIIMIICLKOUT CLIENTEMAC TXGMIIMIICLKIN PHYEMAC GTXCLK CLIENTEMAC TXCLIENTCLKIN EMAC CLIENTTXCLIENTCLKOUT CLIENTEMAC RXCLIENTCLKIN EMAC C...

Page 117: ... in Figure 4 13 It is a requirement to bypass the DCM because the clock frequency of RGMII_RXC_ is 2 5 MHz when operating at 10 Mb s and 2 5 MHz is below the DCM low frequency threshold for Virtex 4 FPGAs However at the 10 Mb s and 100 Mb s operating speeds input setup and hold margins increase appropriately and the input RGMII data can be sampled correctly without use of the DCM The CLIENTEMAC DC...

Page 118: ...N input port and transmitter client logic in the FPGA fabric through a BUFG The receiver client clocking is similar Figure 4 14 Tri Mode RGMII v2 0 Clock Management EMAC PHYEMAC GTXCLK CLIENTEMAC TXGMIIMIICLKIN EMAC CLIENTTXGMIIMIICLKOUT CLIENTEMAC TXCLIENTCLKIN EMAC CLIENTTXCLIENTCLKOUT EMAC PHYTXD 3 0 EMAC PHYTXD 7 4 PHYEMAC MIITXCLK CLIENTEMAC DCMLOCKED CLIENTEMAC RXCLIENTCLKIN EMAC CLIENTRXCLI...

Page 119: ...ement EMAC PHYEMAC GTXCLK CLIENTEMAC TXGMIIMIICLKIN EMAC CLIENTTXGMIIMIICLKOUT CLIENTEMAC TXCLIENTCLKIN EMAC CLIENTTXCLIENTCLKOUT EMAC PHYTXD 3 0 EMAC PHYTXD 7 4 PHYEMAC MIITXCLK CLIENTEMAC DCMLOCKED CLIENTEMAC RXCLIENTCLKIN EMAC CLIENTRXCLIENTCLKOUT GTX_CLK TX Client Logic RX Client Logic BUFG BUFG OBUF IBUF ODDR D1 D2 Q RGMII_TXD_ 3 0 BUFG 1 IDELAY RGMII_IOB_ OBUF RGMII_TXC_ IOBUF ODDR D1 D2 Q 0...

Page 120: ...v1 3 Figure 4 16 shows the tri mode clock management following the Hewlett Packard RGMII specification v1 3 GTX_CLK must be provided to the Ethernet MAC with a high quality 125 MHz clock that satisfies the IEEE Std 802 3 2002 requirements The EMAC CLIENTTXGMIIMIICLKOUT port generates the appropriate frequency deriving from GTX_CLK and depending on the operating frequency of the link It clocks dire...

Page 121: ...CLIENTRXCLIENTCLKOUT EMAC PHYTXD 3 0 EMAC GTX_CLK BUFG TX Client Logic BUFG RX Client Logic OBUF RGMII_TXD_ 3 0 Q D1 PHYEMAC MIITXCLK ODDR D2 EMAC PHYTXD 7 4 Q D1 ODDR D2 OBUF RGMII_TXC_ 1 0 CLIENTEMAC DCMLOCKED UG074_3_67_031009 BUFG 1 PHYEMAC RXCLK PHYEMAC RXD 3 0 PHYEMAC RXD 7 4 Notes 1 A regional buffer BUFR can replace this BUFG Refer to the Virtex 4 User Guide for BUFR usage guidelines CLKIN...

Page 122: ...the PHY RGMII_TXD_ Output Transmits the first 4 bits of packet data 3 0 on the rising edge of RGMII_TXC_ and the top 4 bits 7 4 on the falling edge TXD is 4 bits wide connecting to the PHY RGMII_TX_CTL_ 1 Output This signal is TXEN on the rising edge of RGMII_TXC_ and an encoded TXERR on the falling edge RGMII_RXC_ Input Recovered clock from data stream by the PHY 125 MHz 25 MHz or 2 5 MHz RGMII_R...

Page 123: ...Capabilities These options are 1 10 100 1000 Mb s clock tolerance compliant with Ethernet specification Default setting provides the implementation using the RX elastic buffer in FPGA fabric This alternative RX elastic buffer utilizes a single block RAM to create a buffer twice as large as the one present in the RocketIO transceivers subsequently consuming extra logic resources However this defaul...

Page 124: ...difference between the two devices can be 200 ppm which translates into a full clock period difference every 5000 clock periods Relating this information to an Ethernet frame there is a single byte of difference every 5000 bytes of received frame data causing the RX elastic buffer to either fill or empty by an occupancy of one The maximum Ethernet frame non jumbo has a 1522 byte size for a VLAN fr...

Page 125: ...n then there are 30 16 14 FIFO locations available before the buffer hits the underflow mark This analysis assumes that the buffer is approximately at the half full level at the start of the frame reception There are as illustrated two locations of uncertainty above and below the exact half full mark of 32 The uncertainty is a result of the clock correction decision which is performed in a differe...

Page 126: ...duration of frame reception If the buffer is filling during frame reception then there are 122 66 56 FIFO locations available before the buffer hits the overflow mark If the buffer is emptying during reception then there are 62 6 56 FIFO locations available before the buffer hits the underflow mark This analysis assumes that the buffer is approximately at the half full level at the start of the fr...

Page 127: ...e FPGA Logic RX elastic buffer implementation if they have any doubts to reliable operation Closely Related Clock Sources Two cases are described with closely related clocks in SGMII mode Case 1 Figure 4 20 illustrates a simplified diagram of a common situation where the Ethernet MAC in SGMII mode is interfaced to an external PHY device A common oscillator source is used for both the FPGA and the ...

Page 128: ...ds and resulting in a requirement for 16 FIFO entries above and below the half full point This case provides reliable operation with the MGT RX elastic buffers However the designer must check the PHY data sheet to ensure that the PHY device sources the receiver SGMII stream synchronously to its reference oscillator Using the FPGA Logic Elastic Buffer Figure 4 21 illustrates a simplified diagram of...

Page 129: ...onfigured in SGMII Mode Ethernet MAC PCS PMA Sublayer MGTCLK_P RXP_ RXN_ TXP_ TXN_ UG194_6_29_103106 EMAC PHYPOWERDOWN EMAC PHYTXCHARDISPMODE EMAC PHYTXCHARDISPVAL EMAC PHYTXCHARISK EMAC PHYTXD 7 0 EMAC PHYLOOPBACKMSB PHYEMAC COL EMAC PHYSYNCACQSTATUS PHYEMAC RXBUFSTATUS 0 PHYEMAC RXBUFFERR PHYEMAC RXCHARISCOMMA PHYEMAC RXCHARISK PHYEMAC RXCHECKINGCRC PHYEMAC RXBUFSTATUS 1 PHYEMAC RXCOMMADET PHYEM...

Page 130: ...RSTBYTE EMAC CLIENTTXCOLLISION HOSTADDR 9 0 HOSTCLK HOSTMIIMSEL HOSTOPCODE 1 0 HOSTREQ HOSTMIIMRDY HOSTRDDATA 31 0 HOSTWRDATA 31 0 DCREMACENABLE EMACDCRACK EMACDCRDBUS 0 31 EMAC CLIENTRXSTATS 6 0 EMAC CLIENTRXSTATSBYTEVLD EMAC CLIENTRXSTATSVLD CLIENTEMAC TXD 15 0 CLIENTEMAC TXDVLD CLIENTEMAC TXDVLDMSW EMAC CLIENTTXACK EMAC CLIENTTXRETRANSMIT EMAC CLIENTTXSTATS EMAC CLIENTTXSTATSBYTEVLD EMAC CLIENT...

Page 131: ...e clock with a frequency of 250 MHz specifically for the MGT The output SYNCLK1OUT connects to the PLL reference clock input REFCLK1 TXOUTCLK1 is derived from the transmitter PLL TXOUTCLK1 feeds TXUSRCLK2 and the PHYEMAC GTXCLK RXRECCLK1 feeds a BUFR that is used to clock the internal elastic buffer This buffer is only necessary for SGMII The output of the BUFR also drives RXUSRCLK2 RXUSRCLK and T...

Page 132: ...lign to commas LOOPBACKMSB_ Output Loopback tests within the MGTs MGTRXRESET_ Output Reset to receive PCS of MGT MGTTXRESET_ Output Reset to transmit PCS of MGT POWERDOWN_ Output Power down the MGTs SYNC_ACQ_STATUS_ Output The output from the receiver s synchronization state machine of IEEE Std 802 3 Clause 36 When asserted High synchronization on the received bitstream is obtained The state machi...

Page 133: ...High to enable correct operation the Ethernet MAC TXBUFERR_ Input TX buffer error overflow or underflow CLIENTEMAC DCMLOCKED Input If a DCM is used to derive any of the clock signals going to the Ethernet MAC the locked port of the DCM must be connected to the CLIENTEMAC DCMLOCKED port of the Ethernet MAC The Ethernet MAC is held in reset until CLIENTEMAC DCMLOCKED is driven to logic 1 If DCM is n...

Page 134: ...GMII specification Table 4 7 SGMII Auto Negotiation Advertisement Register Register 4 Bit s Name Description Attributes Default Value 4 15 0 All bits SGMII defined value sent from the MAC to the PHY Read Only 000000000000001 Table 4 8 SGMII Auto Negotiation Link Partner Ability Base Register Register 5 Bit s Name Description Attributes Default Value 5 15 Link up down 1 Link up 0 Link down Read onl...

Page 135: ...on The host interface can control the MDIO interface as defined in MDIO Interface in Chapter 3 When the management interface is not present the PCS sublayer management register block must be accessed using a separate MDIO controller outside the Ethernet MAC The MGT provides some of the PCS layer functionality including 8B 10B encoding and decoding and serialization and deserialization in the PMA l...

Page 136: ...STREQ HOSTMIIMRDY HOSTRDDATA 31 0 HOSTWRDATA 31 0 DCREMACENABLE EMACDCRACK EMACDCRDBUS 0 31 EMAC CLIENTRXSTATS 6 0 EMAC CLIENTRXSTATSBYTEVLD EMAC CLIENTRXSTATSVLD CLIENTEMAC TXD 15 0 CLIENTEMAC TXDVLD CLIENTEMAC TXDVLDMSW EMAC CLIENTTXACK EMAC CLIENTTXRETRANSMIT EMAC CLIENTTXSTATS EMAC CLIENTTXSTATSBYTEVLD EMAC CLIENTTXSTATSVLD HOSTEMAC1SEL CLIENTEMAC PAUSEREQ CLIENTEMAC PAUSEVAL 15 0 CLIENTEMAC T...

Page 137: ...nects to the PLL reference clock input REFCLK TXOUTCLK1 derived from the transmitter PLL reflects the reference clock and drives the other clock inputs It connects through a global buffer to PHYEMAC GTXCLK and into TXUSRCLK2 and RXUSRCLK2 TXUSRCLK and RXUSRCLK are not used and are tied to ground To ensure that the Ethernet MAC does not operate until the MGT has achieved all necessary locks the CLI...

Page 138: ...E X PCS PMA 8 bit Data Client Clock Management UG074_3_80_030907 GT11 GT11CLK_MGT MGTCLKP MGTCLKN SYNCLK1OUT REFCLK1 RXUSRCLK2 RXUSRCLK 0 250 MHz BUFG TXUSRCLK2 TXOUTCLK1 TXUSRCLK 0 EMAC PHYEMAC GTXCLK CLIENTEMAC TXCLIENTCLKIN EMAC CLIENTTXCLIENTCLKOUT CLIENTEMAC RXCLIENTCLKIN EMAC CLIENTRXCLIENTCLKOUT Client Logic X X www BDTIC com XILINX ...

Page 139: ...cy of 250 MHz for 1 25 Gb s and 2 5 Gb s line rates The output SYNCLK1OUT connects to the PLL reference clock input REFCLK1 TXOUTCLK1 Figure 4 28 1000BASE X PCS PMA 16 Bit Data Client Clock Management UG074_3_64_012408 GT11 GT11CLK_MGT MGTCLKP MGTCLKN SYNCLK1OUT REFCLK1 RXUSRCLK2 RXUSRCLK 0 250 MHz BUFG TXUSRCLK2 TXOUTCLK1 RXLOCK TXLOCK TXUSRCLK 0 Ethernet MAC DCM User Application BUFG BUFG X CLIE...

Page 140: ...locked signals from the client interface DCM are ANDed together to generate a combined lock signal for CLIENTEMAC DCMLOCKED The lock signal ensures the Ethernet MAC does not operate until the MGT has achieved all the necessary locks The phase matched clock divider PMCD feature of certain Virtex 4 devices can be used to replace the client interface DCM PCS PMA Signals An Ethernet MAC wrapper has al...

Page 141: ...000000 Table 4 10 Control Register Register 0 Cont d Bit s Name Description Attributes Default Value Table 4 11 Status Register Register 1 Bit s Name Description Attributes Default Value 1 15 100BASE T4 The Ethernet MAC always returns a 0 for this bit because 100BASE T4 is not supported Returns 0 0 1 14 100BASE X Full Duplex The Ethernet MAC always returns a 0 for this bit because 100BASE X full d...

Page 142: ... is not supported Returns 0 0 1 0 Extended Capability The Ethernet MAC always returns a 0 for this bit because no extended register set is supported Returns 0 0 Notes 1 When High the link is valid synchronization of the link has been obtained and Auto Negotiation if present and enabled has completed When Low a valid link has not been established Either link synchronization has failed or Auto Negot...

Page 143: ...ed Read Write 0 4 14 Reserved Always returns 0 writes ignored Returns 0 0 4 13 12 Remote Fault 00 No error 01 Offline 10 Link failure 11 Auto negotiation error Read Write Self clearing to 00 after auto negotiation 00 4 11 9 Reserved Always return 0 writes ignored Returns 0 0 4 8 7 Pause 00 No PAUSE 01 Symmetric PAUSE 10 Asymmetric PAUSE towards link partner 11 Both symmetric PAUSE and asymmetric P...

Page 144: ...00 No PAUSE 01 Symmetric PAUSE supported 10 Asymmetric PAUSE supported 11 Both symmetric PAUSE and asymmetric PAUSE supported Read Only 00 5 6 Half Duplex 1 Half duplex mode is supported 0 Half duplex mode is not supported Read Only 0 5 5 Full Duplex 1 Full duplex mode is supported 0 Full duplex mode is not supported Read Only 0 5 4 0 Reserved Always returns 0s Returns 0s 00000 Table 4 15 Auto Neg...

Page 145: ...onal Next Page s follow 0 Last page Read Only 0 8 14 Acknowledge Used by auto negotiation function to indicate reception of a link partner s base or next page Read Only 0 8 13 Message Page 1 Message Page 0 Unformatted Page Read Only 0 8 12 Acknowledge 2 1 Complies with message 0 Cannot comply with message Read Only 0 8 11 Toggle Value toggles between subsequent next pages Read Only 0 8 10 0 Messag...

Page 146: ...9 Vendor Specific Register Auto Negotiation Interrupt Control Register Register 16 Bit s Name Description Attributes Default Value 16 15 2 Reserved Always returns 0s Returns 0s 00000000000000 16 1 Interrupt Status 1 Interrupt is asserted 0 Interrupt is not asserted If the interrupt is enabled this bit is asserted upon the completion of an auto negotiation cycle it can only be cleared by writing 0 ...

Page 147: ...neration module of the Ethernet MAC Table 5 1 Transmit Clock Speeds PHYEMAC GTXCLK Clock Signals Direction 1000 Mb s 100 Mb s 10 Mb s PHYEMAC GTXCLK Input 125 MHz 125 MHz 125 MHz Table 5 2 Receive Clock Speeds PHYEMAC RXCLK Clock Signals Direction 1000 Mb s 100 Mb s 10 Mb s PHYEMAC RXCLK Input 125 MHz 25 MHz 2 5 MHz Table 5 3 Client Clock Frequency Data Rate Direction 1000 Mb s 100 Mb s 10 Mb s EM...

Page 148: ...IN The CLIENTEMAC TXGMIIMIICLKIN signal runs the MII GMII RGMII logic inside the Ethernet MAC This clock signal must be from the FPGA clock drivers BUFG of EMAC CLIENTTXGMIIMIICLKOUT When Ethernet MAC is configured in SGMII or 1000BASE X mode TX_GMII_MII_CLK is driven by PHYEMAC GTXCLK and the CLIENTEMAC TXGMIIMIICLKIN clock is not used When configured in MII mode EMAC CLIENTTXGMIIMIICLKOUT is der...

Page 149: ...AC RXCLK and used to run the MII GMII RGMII sublayer When the Ethernet MAC is configured in either SGMII or 1000BASE X PCS PMA mode the clock to run the PCS PMA sublayer is generated from the PHYEMAC GTXCLK See Chapter 4 Physical Interface for clock usage Ethernet MAC Configuration The Ethernet MAC can be configured using hardware or by accessing the registers through the host interface in softwar...

Page 150: ... Address Word 0 0x384 Unicast Address Word 1 0x388 Multicast Address Table Access Word 0 0x38C Multicast Address Table Access Word 1 0x390 Address Filter Mode EMAC1 0x600 Receiver Configuration Word 0 0x640 Receiver Configuration Word 1 0x680 Transmitter Configuration 0x6C0 Flow Control Configuration 0x700 Ethernet MAC Mode Configuration 0x720 RGMII SGMII Configuration 0x740 Management Configurati...

Page 151: ...ner The operation of the 1000BASE X auto negotiation is summarized 1 To enable auto negotiation both auto negotiation see Table 4 10 Control Register Register 0 and MDIO see Table 3 14 Management Configuration Register must be enabled Then auto negotiation automatically starts After power up reset or enabling of the MDIO interface Upon loss of synchronization Whenever the link partner initiates au...

Page 152: ...tached Ethernet MAC should be configured accordingly There are two methods by which a host processor may learn of the competition of an auto negotiation cycle By polling the auto negotiation completion bit 1 5 in Register 1 see Table 4 11 Status Register Register 1 By using the auto negotiation interrupt port see Using the Auto Negotiation Interrupt page 153 SGMII Standard Figure 5 4 illustrates t...

Page 153: ...00BASE X Auto Negotiation Overview page 151 Auto Negotiation Link Timer The built in auto negotiation Link Timer has different durations for different standards 1000BASE X Standard The 1000BASE X standard Link Timer is defined as having a duration somewhere between 10 354 ms and 10 387 ms SGMII Standard The SGMII standard Link Timer is defined as having a duration of 1 606 ms to 1 638 ms Using the...

Page 154: ...154 www xilinx com Embedded Tri Mode Ethernet MAC User Guide UG074 v2 2 February 22 2010 Chapter 5 Miscellaneous Functions R www BDTIC com XILINX ...

Page 155: ...erilog wrappers are generated by the CORE Generator tool in the ISE software as well as the scripts to simulate the Secure IP model For further help using the Ethernet MAC SecureIP model see the documentation supplied with ISE software especially the Synthesis and Simulation Design Guide at http www xilinx com support software_manuals htm Model Considerations The DCR bus except for DCREMACENABLE i...

Page 156: ...wing guidelines to improve design timing using the Virtex 4 FPGA Embedded Tri Mode Ethernet MAC If available use dedicated global clock pins for the Ethernet MAC input clocks Use the column of IOBs located closest to the PowerPC processor and Ethernet MAC block Use the MGTs located closest to the PowerPC processor and Ethernet MAC block www BDTIC com XILINX ...

Page 157: ...alue of the Ethernet MAC configuration register Assuming the DCR base address is 0x0 to read from the EMAC0 transmitter configuration register EMAC Configuration Register 0x280 EMAC0 Transmitter Configuration Write the address of EMAC0 Transmitter Configuration register to the cntlReg register mtdcr 0x0 14 0x280 Poll the RDYstatus register while mfdcr 0x0 15 0x00000020 Read the dataRegLSW with the...

Page 158: ... the address filter configuration registers 1 Write to dataRegLSW register the read mask bit to read the multicast address table register with the respective register being accessed there are four multicast address table registers in the address filter block 2 Write to cntlReg register with the address register of multicast address 0x38C for EMAC0 and 0x78C for EMAC1 Set the Write enable bit to wr...

Page 159: ... the address of EMAC1 Multicast Address Word 0 register to the cntlReg register mtdcr 0x0 14 0x8788 Poll the RDYstatus register while mfdcr 0x0 15 0x00001000 MULTI_ADDR Register 1 of AF Block Write the multicast address 47 32 with the MULTI_ADDR write mask bit to the dataRegLSW register mtdcr 0x0 13 0x0081FACE Write the address of EMAC1 Multicast Address Word 1 register to the cntlReg register mtd...

Page 160: ...with the data to be written to the PHY register 5 Write to the cntlReg register the decode address for MDIO write data 6 Write to the dataRegLSW register with the PHY address and register to be accessed 7 Write to the cntlReg register the decode address for MDIO address output with the Write Enable mask asserted 8 Poll the RDYstatus register until the MDIO write ready bit is asserted Assume the DC...

Page 161: ...thernet MAC configuration registers Conflicts with MDIO register access are avoided by only accessing statistics counters when the signal HOSTMIIMSEL is at logic 0 Implementation of the addressing scheme shown in Table 6 1 ensures that the host bus can be shared without contention This scheme provides space to address 512 statistics counters per Ethernet MAC using addresses 0x000 to 0x1FF Figure 6...

Page 162: ...t_rd_data 31 0 txclientclkin clienttxstats clienttxstatsvld rxclientclkin clienttxstatsvld 6 0 clientrxstatsvld clienttxstatsbytevalid clientrxstatsbytevalid CLIENTEMAC0TXCLIENTCLKIN EMAC0CLIENTTXSTATS EMAC0CLIENTTXSTATSVLD CLIENTEMAC0RXCLIENTCLKIN EMAC0CLIENTRXSTATS 6 0 EMAC0CLIENTRXSTATSVLD EMAC0CLIENTRXSTATSBYTEVLD EMAC0CLIENTTXSTATSBYTEVLD LogiCORE Ethernet Statistics Example Design host_clk h...

Page 163: ...gisters in this address code region the DCR bridge translates the DCR commands into generic host read signals on the host bus I O signals The DCR transaction is encoded on the host bus signals HOSTRDDATA 31 0 and HOSTMIIMRDY as described in Table 6 2 and Figure 6 2 These signals can access statistics counters in the same way as if a standalone host bus is used The statistics values read from stati...

Page 164: ...k Figure 6 3 illustrates how to connect LogiCORE Ethernet Statistics blocks to both Ethernet MACs within the Ethernet MAC block If statistics are required for only one Ethernet MAC then the multiplexing between the statistics cores is simply replaced with a straight through connection Figure 6 2 Statistics Register Read Timing host_clk HOSTRDDATA 8 0 HOSTRDDATA 9 HOSTRDDATA 15 HOSTMIIMRDY HOSTWRDA...

Page 165: ...xstatsvld rxclientclkin clienttxstatsvld 6 0 clientrxstatsvld clienttxstatsbytevalid clientrxstatsbytevalid CLIENTEMAC0TXCLIENTCLKIN EMAC0CLIENTTXSTATS EMAC0CLIENTTXSTATSVLD CLIENTEMAC0RXCLIENTCLKIN EMAC0CLIENTRXSTATS 6 0 EMAC0CLIENTRXSTATSVLD EMAC0CLIENTRXSTATSBYTEVLD EMAC0CLIENTTXSTATSBYTEVLD LogiCORE Ethernet Statistics Example Design host_clk host_addr 8 0 host_addr 9 host_req host_miim_sel ho...

Page 166: ...166 www xilinx com Embedded Tri Mode Ethernet MAC User Guide UG074 v2 2 February 22 2010 Chapter 6 Use Models R www BDTIC com XILINX ...

Page 167: ...r options Provides user configurable Ethernet MAC physical interfaces Supports MII GMII RGMII v1 3 RGMII v2 0 SGMII and 1000BASE X PCS PMA interfaces Provides off chip connections for physical interfaces by instantiating RocketIO transceivers and logic as required for the selected physical interfaces Provides an optimized clocking scheme for the selected physical interface and instantiates the req...

Page 168: ...s module to the DCM reset pins This can be achieved by connecting the reset_200ms_ signal to the reset_200ms_in_ signal at any level of example design HDL hierarchy See the block level wrapper file for more information For further details on the Ethernet MAC wrappers refer to DS307 Virtex 4 Embedded Tri Mode Ethernet MAC Wrapper Data Sheet and GSG240 Virtex 4 Embedded Tri Mode Ethernet MAC Wrapper...

Page 169: ...block Table 2 4 page 25 briefly describes the clock signals necessary to drive the Virtex 4 FPGA Embedded Tri Mode Ethernet MAC Timing Parameters Parameter designations are constructed to reflect the functions they perform as well as the I O signals to which they are synchronous The following subsections explain the meaning of each of the basic timing parameter designations used in Table A 1 throu...

Page 170: ...e All clock cycles refer to cycles of the appropriate TX or RX client interface clock Transmit Path Latency The transmit path latency is measured by counting the number of clock cycles between a data byte being placed on the client interface and its appearance at the PHY interface of the Ethernet MAC For RGMII GMII MII at all speeds the latency is 13 clock cycles SGMII has a latency of 13 clock cy...

Page 171: ...haracteristics on page 172 Table A 4 PHYEMAC GTXCLK Switching Characteristics on page 173 Table A 5 PHYEMAC MIITXCLK Switching Characteristics on page 174 Table A 6 PHYEMAC RXCLK Switching Characteristics on page 174 Figure A 1 Ethernet MAC Timing Relative to Clock Edge Table A 1 CLIENTEMAC RXCLIENTCLKIN Switching Characteristics Parameter Function Signal Clock To Out Tmaccko_ERROR Data Output EMA...

Page 172: ...p CLIENTEMAC TXFIRSTBYTE Tmacckd_DELAY Data Hold CLIENTEMAC TXIFGDELAY Tmacdck_DELAY Data Setup CLIENTEMAC TXIFGDELAY Tmacckd_ERROR Data Hold CLIENTEMAC TXUNDERRUN Tmacdck_ERROR Data Setup CLIENTEMAC TXUNDERRUN Clock To Out Tmaccko_IRQ Data Output EMAC CLIENTANINTERRUPT Tmaccko_ACK Data Output EMAC CLIENTTXACK Tmaccko_CLKOUT Data Output EMAC CLIENTTXCLIENTCLKOUT Tmaccko_ERROR Data Output EMAC CLIE...

Page 173: ... 4 PHYEMAC GTXCLK Switching Characteristics Parameter Function Signal Setup and Hold Relative to Clock Tmacckd_MDIN Data Hold PHYEMAC MDIN Tmacdck_MDIN Data Setup PHYEMAC MDIN Tmacckd_ERROR Data Hold PHYEMAC RXBUFERR Tmacdck_ERROR Data Setup PHYEMAC RXBUFERR Tmacckd_STATUS Data Hold PHYEMAC RXBUFSTATUS Tmacdck_STATUS Data Setup PHYEMAC RXBUFSTATUS Tmacckd_COMMA Data Hold PHYEMAC RXCHARISCOMMA Tmac...

Page 174: ... Tmaccko_SYNC Data Output EMAC PHYSYNCACQSTATUS Tmaccko_DISP Data Output EMAC PHYTXCHARDISPMODE Tmaccko_DISP Data Output EMAC PHYTXCHARDISPVAL Tmaccko_CHAR Data Output EMAC PHYTXCHARISK Table A 5 PHYEMAC MIITXCLK Switching Characteristics Parameter Function Signal Clock To Out Tmaccko_TXCLK Data Output EMAC PHYTXCLK Tmaccko_TXD Data Output EMAC PHYTXD Tmaccko_EN Data Output EMAC PHYTXEN Tmaccko_ER...

Page 175: ...Out Tmaccko_RXD Data Output EMAC CLIENTRXDVREG Tmaccko_STATS Data Output EMAC CLIENTRXSTATS Tmaccko_VALID Data Output EMAC CLIENTRXSTATSBYTEVLD Tmaccko_VALID Data Output EMAC CLIENTRXSTATSVLD Tmaccko_RESET Data Output EMAC PHYMGTRXRESET Tmaccko_VALID Data Output EMAC1CLIENTRXDVLD Tmaccko_VALID Data Output EMAC1CLIENTRXDVLDMSW Tmaccko_VALID Data Output EMAC1CLIENTRXDVREG Table A 6 PHYEMAC RXCLK Swi...

Page 176: ...176 www xilinx com Embedded Tri Mode Ethernet MAC User Guide UG074 v2 2 February 22 2010 Appendix A Ethernet MAC Timing Model R www BDTIC com XILINX ...

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