VCU1525 Acceleration Platform User Guide
69
UG1268 (v1.0) November 13, 2017
Appendix A:
Master Constraints File Listing
set_property PACKAGE_PIN AU20 [get_ports QSFP1_FS1];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP1_FS1];
set_property PACKAGE_PIN AV21 [get_ports QSFP1_INTL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP1_INTL_LS];
set_property PACKAGE_PIN AV22 [get_ports QSFP1_LPMODE_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP1_LPMODE_LS];
set_property PACKAGE_PIN BC19 [get_ports QSFP1_MODPRSL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP1_MODPRSL_LS];
set_property PACKAGE_PIN AY20 [get_ports QSFP1_MODSKLL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP1_MODSKLL_LS];
set_property PACKAGE_PIN AR21 [get_ports QSFP1_REFCLK_RESET];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP1_REFCLK_RESET];
set_property PACKAGE_PIN BC18 [get_ports QSFP1_RESETL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP1_RESETL_LS];
# USB UART
set_property PACKAGE_PIN BB20 [get_ports USB_UART_RX];
set_property IOSTANDARD LVCMOS12 [get_ports USB_UART_RX];
set_property PACKAGE_PIN BF18 [get_ports USB_UART_TX];
set_property IOSTANDARD LVCMOS12 [get_ports USB_UART_TX];
# USER GPIO
# DIP SW3 4-POLE (ACTIVE LOW)
set_property PACKAGE_PIN AN22 [get_ports SW_DP0];
set_property IOSTANDARD LVCMOS12 [get_ports SW_DP0];
set_property PACKAGE_PIN AM19 [get_ports SW_DP1];
set_property IOSTANDARD LVCMOS12 [get_ports SW_DP1];
set_property PACKAGE_PIN AL19 [get_ports SW_DP2];
set_property IOSTANDARD LVCMOS12 [get_ports SW_DP2];
set_property PACKAGE_PIN AP20 [get_ports SW_DP3];
set_property IOSTANDARD LVCMOS12 [get_ports SW_DP3];
# LED DS3 (LED0=R, LED1=Y, LED2=G) FRONTPANEL
set_property PACKAGE_PIN BC21 [get_ports STATUS_LED0_FPGA];
set_property IOSTANDARD LVCMOS12 [get_ports STATUS_LED0_FPGA];
set_property PACKAGE_PIN BB21 [get_ports STATUS_LED1_FPGA];
set_property IOSTANDARD LVCMOS12 [get_ports STATUS_LED1_FPGA];
set_property PACKAGE_PIN BA20 [get_ports STATUS_LED2_FPGA];
set_property IOSTANDARD LVCMOS12 [get_ports STATUS_LED2_FPGA];
#GPIO PB SW1 (ASSIGNED AS CPU_RESETn)
set_property PACKAGE_PIN AL20 [get_ports CPU_RESET_FPGA];
set_property IOSTANDARD LVCMOS12 [get_ports CPU_RESET_FPGA];
# GPIO TEST POINT (PAD WITH 49.9 OHM TO GND)
set_property PACKAGE_PIN AN19 [get_ports TESTCLK_OUT];
set_property IOSTANDARD LVCMOS12 [get_ports TESTCLK_OUT];
# GPIO I2C U2 EXPANSION PORT 0
set_property PACKAGE_PIN AL21 [get_ports SW_SET1_FPGA];
set_property IOSTANDARD LVCMOS12 [get_ports SW_SET1_FPGA];
# I2C MAIN
set_property PACKAGE_PIN BF19 [get_ports I2C_MAIN_RESET_B_LS];
set_property IOSTANDARD LVCMOS12 [get_ports I2C_MAIN_RESET_B_LS];
set_property PACKAGE_PIN BF20 [get_ports I2C_MAIN_SCL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports I2C_MAIN_SCL_LS];
set_property PACKAGE_PIN BF17 [get_ports I2C_MAIN_SDA_LS];
set_property IOSTANDARD LVCMOS12 [get_ports I2C_MAIN_SDA_LS];
