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Xilinx VCU1525, User Manual

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Xilinx VCU1525 User Manual Download Page 54

VCU1525 Acceleration Platform User Guide

54

UG1268 (v1.0) November 13, 2017

www.xilinx.com

Appendix A:

Master Constraints File Listing

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_ADR17];

set_property  PACKAGE_PIN  AU24  [get_ports DDR4_C1_BA0];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_BA0];

set_property  PACKAGE_PIN  AP26  [get_ports DDR4_C1_BA1];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_BA1];

set_property  PACKAGE_PIN  BC22  [get_ports DDR4_C1_BG0];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_BG0];

set_property  PACKAGE_PIN  AW26  [get_ports DDR4_C1_BG1];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_BG1];

set_property  PACKAGE_PIN  AU25  [get_ports DDR4_C1_CK_C0];

set_property  IOSTANDARD  DIFF_SSTL12_DCI  [get_ports DDR4_C1_CK_C0];

set_property  PACKAGE_PIN  AT25  [get_ports DDR4_C1_CK_T0];

set_property  IOSTANDARD  DIFF_SSTL12_DCI  [get_ports DDR4_C1_CK_T0];

set_property  PACKAGE_PIN  BB25  [get_ports DDR4_C1_CKE0];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_CKE0];

set_property  PACKAGE_PIN  AV26  [get_ports DDR4_C1_CK_C1];

set_property  IOSTANDARD  DIFF_SSTL12_DCI  [get_ports DDR4_C1_CK_C1];

set_property  PACKAGE_PIN  AU26  [get_ports DDR4_C1_CK_T1];

set_property  IOSTANDARD  DIFF_SSTL12_DCI  [get_ports DDR4_C1_CK_T1];

set_property  PACKAGE_PIN  BB24  [get_ports DDR4_C1_CKE1];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_CKE1];

set_property  PACKAGE_PIN  AT23  [get_ports DDR4_C1_PAR];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_PAR];

set_property  PACKAGE_PIN  AW25  [get_ports DDR4_C1_ACT_B];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_ACT_B];

set_property  PACKAGE_PIN  AY26  [get_ports DDR4_C1_ALERT_B];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_ALERT_B];

set_property  PACKAGE_PIN  AN18  [get_ports DDR4_C1_EVENT_B];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_EVENT_B];

set_property  PACKAGE_PIN  AR17  [get_ports DDR4_C1_RESET_N];

set_property  IOSTANDARD  LVCMOS12  [get_ports DDR4_C1_RESET_N];

set_property  PACKAGE_PIN  AV23  [get_ports DDR4_C1_CS_B0];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_CS_B0];

set_property  PACKAGE_PIN  AP25  [get_ports DDR4_C1_CS_B1];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_CS_B1];

set_property  PACKAGE_PIN  AR23  [get_ports DDR4_C1_CS_B2];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_CS_B2];

set_property  PACKAGE_PIN  AP23  [get_ports DDR4_C1_CS_B3];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_CS_B3];

set_property  PACKAGE_PIN  AW23  [get_ports DDR4_C1_ODT0];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_ODT0];

set_property  PACKAGE_PIN  AP24  [get_ports DDR4_C1_ODT1];

set_property  IOSTANDARD  SSTL12_DCI  [get_ports DDR4_C1_ODT1];

set_property  PACKAGE_PIN  BD9  [get_ports DDR4_C1_DQ0];

set_property  IOSTANDARD  POD12_DCI  [get_ports DDR4_C1_DQ0];

set_property  PACKAGE_PIN  BD7  [get_ports DDR4_C1_DQ1];

set_property  IOSTANDARD  POD12_DCI  [get_ports DDR4_C1_DQ1];

set_property  PACKAGE_PIN  BC7  [get_ports DDR4_C1_DQ2];

set_property  IOSTANDARD  POD12_DCI  [get_ports DDR4_C1_DQ2];

set_property  PACKAGE_PIN  BD8  [get_ports DDR4_C1_DQ3];

set_property  IOSTANDARD  POD12_DCI  [get_ports DDR4_C1_DQ3];

set_property  PACKAGE_PIN  BD10  [get_ports DDR4_C1_DQ4];

set_property  IOSTANDARD  POD12_DCI  [get_ports DDR4_C1_DQ4];

set_property  PACKAGE_PIN  BE10  [get_ports DDR4_C1_DQ5];

set_property  IOSTANDARD  POD12_DCI  [get_ports DDR4_C1_DQ5];

set_property  PACKAGE_PIN  BE7  [get_ports DDR4_C1_DQ6];

set_property  IOSTANDARD  POD12_DCI  [get_ports DDR4_C1_DQ6];

set_property  PACKAGE_PIN  BF7  [get_ports DDR4_C1_DQ7];

set_property  IOSTANDARD  POD12_DCI  [get_ports DDR4_C1_DQ7];

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Summary of Contents for VCU1525

Page 1: ...VCU1525 Reconfigurable Acceleration Platform User Guide UG1268 v1 0 November 13 2017...

Page 2: ...Platform User Guide 2 UG1268 v1 0 November 13 2017 www xilinx com Revision History The following table shows the revision history for this document Date Version Revision 11 13 2017 1 0 Initial Xilinx...

Page 3: ...12 FPGA Configuration 12 Chapter 3 Board Component Descriptions Overview 15 Component Descriptions 15 Virtex UltraScale XCVU9P L2FSGD2104E FPGA 15 I O Voltage Rails 15 DDR4 DIMM Memory 17 Quad SPI Fl...

Page 4: ...Constraints File Listing Overview 47 Appendix B Regulatory and Compliance Information Overview 71 Declaration of Conformity 71 Directives 71 Standards 71 Electromagnetic Compatibility 72 Safety 72 Ma...

Page 5: ...4E FPGA This Xilinx FPGA based PCIe accelerator board is designed to accelerate compute intensive applications like machine learning data analytics and video processing The VCU1525 board is available...

Page 6: ...oling In either cooling configuration due to the board enclosure switches are not accessible nor are LEDs visible except the triple LED module DS3 which protrudes through the left front end PCIe brack...

Page 7: ...R4 16 GB 2400 mega transfers per second MT s 64 bit with error correcting code ECC DIMM X Ref Target Figure 1 3 Figure 1 3 VCU1525 Board Block Diagram 244 pin DIMM interface 64 bit ECC dual rank suppo...

Page 8: ...C bus Status LEDs User I O 4 pole user dual inline package DIP SW3 CPU_RESET PB SW1 Power management with system management bus SMBus voltage current and temperature monitoring Dynamic power sourcing...

Page 9: ...s Dimensions Height 4 2 inch 10 67 cm Thickness 5 0 062 inch 0 157 cm Length 9 13 inch 23 19 cm Note A 3D model of this board is not available Environmental Temperature Operating 0 C to 45 C Storage 2...

Page 10: ...ional description of the component and board features in Chapter 3 Board Component Descriptions IMPORTANT Figure 2 1 is for visual reference only and might not reflect the current revision of the boar...

Page 11: ...n MTA18ASF2G72PZ 2G3B1IG 36 6 U17 Quad SPI Flash Memory 1Gb total Micron MT25QU01GBBA8E12 0SIT 12 7 U27 J13 USB JTAG bridge w USB Micro AB connector FT4232HQ USB UART Interface FTDI FT4232HQ REEL HIRO...

Page 12: ...pins are hardwired to M 2 0 001 Master SPI mode with pull up down resistors 15 U19 Board Management Controller BMC TI MSP432P401RIPZ 24 16 JP1 Auxiliary 12V power connector Vccint Regulator Circuit LI...

Page 13: ...iguration JTAG mode overrides it if invoked JTAG mode is always available independent of the Mode pin settings M0 is pulled up however it is also connected to the I2C I O port U2 PCA9536 device port P...

Page 14: ...Guide 14 UG1268 v1 0 November 13 2017 www xilinx com Chapter 2 Board Setup and Configuration The configuration circuit is shown in Figure 2 2 X Ref Target Figure 2 2 Figure 2 2 VCU1525 Configuration C...

Page 15: ...corresponding detailed functional description in this chapter Component locations are shown in Table 2 1 Component Descriptions Virtex UltraScale XCVU9P L2FSGD2104E FPGA Figure 2 1 callout 1 The VCU1...

Page 16: ...GTY130 MGTY129 MGTY128 MGTY123 MGTY122 MGTY121 MGTY120 72 73 74 71 70 69 66 64 65 61 62 63 67 X19971 103017 Table 3 1 I O Bank Voltage Rails XCVU9P L2FSGD2104E Power Net Name Voltage Connected To Bank...

Page 17: ...traScale Architecture Based FPGAs Memory IP LogiCORE IP Product Guide PG150 Ref 3 The VCU1525 board DDR4 memory interfaces are 40 impedance implementations For more details about the Micron DDR4 DIMM...

Page 18: ...Data rate variable Figure 3 2 shows the linear Quad SPI flash memory circuitry on the VCU1525 board For more flash memory details see the Micron MT25QU01GBB8E12 0SIT data sheet at the Micron website R...

Page 19: ...lled by the BMC to allow only one JTAG connection at a time JTAG configuration is allowed at any time regardless of the FPGA mode pin settings The JTAG chain block diagram is shown in Figure 3 3 For m...

Page 20: ...ngle Micro AB USB connector J13 Channel AD is configured to support the JTAG chain Channel AC implements a 2 wire TX RX UART connection to the MSP432 BMC U19 Channel BD implements a 2 wire level shift...

Page 21: ...m right angle receptacle Amphenol 10125839 04RAEHLF J17 is selectable via TI TS3USB221RSER 1 to 2 USB switch U59 which is controlled by the MSP432 U19 BMC USB switch U59 selects between the Micro AB U...

Page 22: ...USB_DP U27 8 DP FT4232HQ U27 DP 9 S USB_SEL U19 53 P9_1 U59 USB Switch Port Select J17 USB_VBUS2 present USB_PRES U19 24 P10_4 USB J17 pin 1 voltage detection Table 3 4 VCU1525 Board Clock Sources Clo...

Page 23: ...clock buffer USER_SI570_CLOCK_P N GPIO I F bank 64 MGT SI570 CLOCK0 QSFP0 U43 Q2 Silicon Labs Si53340 3 3V LVDS clock buffer USER_SI570_CLOCK0_P N QSFP0 GTY231 REFCLK0 MGT SI570 CLOCK1 QSFP1 U43 Q3 Si...

Page 24: ...K 70 DDR4 C2 I F F32 E32 GC QBC U13Z XCVU9PFSGD2104 Si53340 B GM GTY BANK 231 QSFPO I F U13AL REFCLK1 XCVU9PFSGD2104 REFCLK0 BANK 72 DDR4 C3 I F J16 H16 GC QBC U13X XCVU9PFSGD2104 BANK 64 GPI0 I F U13...

Page 25: ...33MHz 1 8V CMOS output on A only Low phase jitter of 0 7 ps RMS Two outputs of the SI5335A U9 are used CLK0A B The system clock SYSCLK is a LVDS 300MHz clock wired to SI53340 U44 1 to 4 clock buffer w...

Page 26: ...Descriptions The system and QSFP0 clock source Si5335A U9 is shown in Figure 3 6 The 300 MHz clock buffer Si53340 U44 is shown in Figure 3 7 X Ref Target Figure 3 7 Figure 3 7 300MHz and QSFP0 156 25M...

Page 27: ...ng Mode Clock Generator Loop bandwidth 1 6MHz CLK0A 0B 300MHz 1 8V LVDS CLK1A 1B 156 25MHz 1 8V LVDS CLK2A 2B 90MHz 1 8V CMOS output on A only CLK3A 3B 33 333MHz 1 8V CMOS output on A only Low phase j...

Page 28: ...LVDS clock buffer On power up the SI570 user clock defaults to an output frequency of 156 250MHz User applications can change the output frequency within the range of 10MHz to 810 MHz through an inter...

Page 29: ...ck are listed in Appendix A Master Constraints File Listing The USER_SI570 and QSFP0 1 MGT_SI570 clock circuit is shown in Figure 3 9 GTY Transceivers Figure 2 1 callout 1 The VCU1525 board provides a...

Page 30: ...K1 QSFP0_CLOCK_P N Contains four GTY transceivers allocated to QSFP0 TX RX lanes 1 4 Quad 230 MGTREFCLK0 MGT_SI570_CLOCK1_C_P N MGTREFCLK1 QSFP1_CLOCK_P N Contains four GTY transceivers allocated to Q...

Page 31: ...Figure 3 11 Figure 3 11 GTY Bank Assignments BANK 224 MGTY_224_0 MGTY_224_1 MGTY_224_2 MGTY_224_3 MGT_224_REFCLK0 MGT_224_REFCLK1 PEX_TX15 RX15 PEX_TX14 RX14 PEX_TX13 RX13 PEX_TX12 RX12 NC NC BANK 22...

Page 32: ...QSFP Module Connectors Figure 2 1 callout 13 14 The VCU1525 board hosts dual quad 4 channel small form factor pluggable 28 Gb s QSFP connectors QSFP0 J7 QSFP1 J9 that accept 28 Gb s and below QSFP op...

Page 33: ...ion about the quad small form factor pluggable 28 Gb s QSFP module see the SFF 8663 and SFF 8679 specifications for the 28 Gb s QSFP at the SNIA Technology Affiliates website Ref 9 I2C Bus The VCU1525...

Page 34: ...T_B_LS on U13 FPGA pin BF19 and I2C_MAIN_RESET_B on MSP432 U19 pin 79 net must both be driven High to enable I2C bus transactions with the devices connected to U28 and U56 FPGA user applications that...

Page 35: ...36 4 bit port expander and an 8 Kbit M24C08 EEPROM on the IIC_SDA SCL_EEPROM channel 1 I2C bus Also channel 2 supports four DDR4 DIMM sockets on the DDR4_SDA SCL bus Table 3 5 I2C_FPGA_SDA SCL I2C Bus...

Page 36: ...Table 3 6 I2C_MAIN_SDA SCL I2C Bus Addresses MSP432 U19 only I2C Bus I2C Switch Position I2C Address Device Binary Format Hex Format PCA9546 4 channel bus switch Not applicable 0b1110101 0x75 U56 PCA9...

Page 37: ...sting Board Management Controller Figure 2 1 callout 15 The VCU1525 hosts an MSP432P401RIPZ board management controller BMC U19 comprising a MSP432 ARM Cortex microcontroller with integrated ADCs and...

Page 38: ...nnels 8 Timer_A 1 5 5 5 5 eUSCI CHANNEL A UART IrDA SPI 4 CHANNEL B SPI I2C 4 20 mA drive I O 4 Total I Os 84 Package 100 PZ Notes 1 Each number in the sequence represents an instantiation of Timer_A...

Page 39: ...y FPGA CSn SPIx4 QSPI1 SPIx4 CSn CSn SYSMON MSP432 SPI WP I2C I2C GOLDEN IMAGE QSPI2 CSn SPIx4 1 4 MUX QSFP QSFP I2C Bank64 EEPROM SI570 New EEPROM for IP keys QSFP0 QSFP1 BARE METAL User Controlled I...

Page 40: ...November 13 2017 www xilinx com Chapter 3 Board Component Descriptions Figure 3 16 shows the U19 MSP432 circuit See the schematic 0381795 Rev D sheet 24 for finer details Ref 7 X Ref Target Figure 3 1...

Page 41: ...inx com Chapter 3 Board Component Descriptions Figure 3 17 shows the voltage and sense points monitored by the U19 MSP432 See schematic 0381795 Rev D sheet 24 for finer details Ref 7 X Ref Target Figu...

Page 42: ...92 LTC3636 EFF1 92 LTC7150 EFF1 92 LTC7150 EFF1 92 LTC3636 1 2 EFF1 92 LTC3636 2 2 EFF1 90 MGTAVTT VCCBRAM VCCINTIO DDR4_VCC1V2_TOP_DIMMS DDR4_VCC1V2_BTM_DIMMS MGTVCCAUX VCCAUX VCCAUXIO MGTAVCC LT860...

Page 43: ...ble 3 7 is accessed through the 2x5 PMBus connector J1 provided for use with the Linear Technology DC1613A USB to PMbus dongle This cable can be ordered from the Linear Technology website Ref 10 The a...

Page 44: ...432 U19 ADC Channel Assignments Rail Net Name MSP432 U19 Pin Name 12V_PEX ADC0 69 P5_5 A0 3V3_PEX ADC1 68 P5_4 A1 3V3AUX ADC2 67 P5_3 A2 12V_AUX ADC3 66 P5_2 A3 DDR4_VPP_BTM ADC4 65 P5_1 A4 SYS_5V5 AD...

Page 45: ...5 6 enables 12V AUX0 recognition and VCCINT phase 2 3 and 4 come on phase 1 4 max current is 110 amperes Plugging an additional 4 pin 2x2 12V connector into JP1 pins 3 4 7 8 enables 12V AUX1 recognit...

Page 46: ...into the LM96063 device register set The LM96063 has I2C address 0x4B and is accessed through channel 0 of the U56 PCA9546 I2C mux address 0x75 as shown in the I2C Bus section of this document The LM9...

Page 47: ...t_ports SYSCLK0_300_P set_property IOSTANDARD DIFF_SSTL12 get_ports SYSCLK0_300_P set_property PACKAGE_PIN AW19 get_ports SYSCLK1_300_N set_property IOSTANDARD DIFF_SSTL12 get_ports SYSCLK1_300_N set_...

Page 48: ...DR4_C0_ADR3 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C0_ADR3 set_property PACKAGE_PIN AW36 get_ports DDR4_C0_ADR4 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C0_ADR4 set_property PACKAG...

Page 49: ...GE_PIN AT33 get_ports DDR4_C0_EVENT_B set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C0_EVENT_B set_property PACKAGE_PIN AU31 get_ports DDR4_C0_RESET_N set_property IOSTANDARD LVCMOS12 get_ports DD...

Page 50: ...t_ports DDR4_C0_DQ21 set_property PACKAGE_PIN BB34 get_ports DDR4_C0_DQ22 set_property IOSTANDARD POD12_DCI get_ports DDR4_C0_DQ22 set_property PACKAGE_PIN BC34 get_ports DDR4_C0_DQ23 set_property IOS...

Page 51: ..._ports DDR4_C0_DQ51 set_property IOSTANDARD POD12_DCI get_ports DDR4_C0_DQ51 set_property PACKAGE_PIN AV29 get_ports DDR4_C0_DQ52 set_property IOSTANDARD POD12_DCI get_ports DDR4_C0_DQ52 set_property...

Page 52: ...set_property PACKAGE_PIN AM31 get_ports DDR4_C0_DQS_T4 set_property IOSTANDARD DIFF_POD12 get_ports DDR4_C0_DQS_T4 set_property PACKAGE_PIN AL29 get_ports DDR4_C0_DQS_C5 set_property IOSTANDARD DIFF_P...

Page 53: ..._property IOSTANDARD SSTL12_DCI get_ports DDR4_C1_ADR1 set_property PACKAGE_PIN AW24 get_ports DDR4_C1_ADR2 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C1_ADR2 set_property PACKAGE_PIN AN26 get_...

Page 54: ...ARD SSTL12_DCI get_ports DDR4_C1_ALERT_B set_property PACKAGE_PIN AN18 get_ports DDR4_C1_EVENT_B set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C1_EVENT_B set_property PACKAGE_PIN AR17 get_ports DD...

Page 55: ...orts DDR4_C1_DQ21 set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ21 set_property PACKAGE_PIN BA7 get_ports DDR4_C1_DQ22 set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ22 set_property PAC...

Page 56: ...et_ports DDR4_C1_DQ50 set_property PACKAGE_PIN AU17 get_ports DDR4_C1_DQ51 set_property IOSTANDARD POD12_DCI get_ports DDR4_C1_DQ51 set_property PACKAGE_PIN BB17 get_ports DDR4_C1_DQ52 set_property IO...

Page 57: ...t_property IOSTANDARD DIFF_POD12 get_ports DDR4_C1_DQS_C4 set_property PACKAGE_PIN BE12 get_ports DDR4_C1_DQS_T4 set_property IOSTANDARD DIFF_POD12 get_ports DDR4_C1_DQS_T4 set_property PACKAGE_PIN BC...

Page 58: ..._C2_ADR0 set_property PACKAGE_PIN A33 get_ports DDR4_C2_ADR1 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C2_ADR1 set_property PACKAGE_PIN C33 get_ports DDR4_C2_ADR2 set_property IOSTANDARD SSTL1...

Page 59: ...IN F30 get_ports DDR4_C2_ALERT_B set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C2_ALERT_B set_property PACKAGE_PIN D40 get_ports DDR4_C2_EVENT_B set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C...

Page 60: ...t_ports DDR4_C2_DQ20 set_property PACKAGE_PIN G26 get_ports DDR4_C2_DQ21 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DQ21 set_property PACKAGE_PIN F28 get_ports DDR4_C2_DQ22 set_property IOSTA...

Page 61: ...t_ports DDR4_C2_DQ50 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DQ50 set_property PACKAGE_PIN K33 get_ports DDR4_C2_DQ51 set_property IOSTANDARD POD12_DCI get_ports DDR4_C2_DQ51 set_property...

Page 62: ...set_property PACKAGE_PIN E40 get_ports DDR4_C2_DQS_C4 set_property IOSTANDARD DIFF_POD12 get_ports DDR4_C2_DQS_C4 set_property PACKAGE_PIN E39 get_ports DDR4_C2_DQS_T4 set_property IOSTANDARD DIFF_POD...

Page 63: ...R0 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C3_ADR0 set_property PACKAGE_PIN B15 get_ports DDR4_C3_ADR1 set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C3_ADR1 set_property PACKAGE_PIN F14...

Page 64: ...TL12_DCI get_ports DDR4_C3_ACT_B set_property PACKAGE_PIN G15 get_ports DDR4_C3_ALERT_B set_property IOSTANDARD SSTL12_DCI get_ports DDR4_C3_ALERT_B set_property PACKAGE_PIN D18 get_ports DDR4_C3_EVEN...

Page 65: ...orts DDR4_C3_DQ20 set_property IOSTANDARD POD12_DCI get_ports DDR4_C3_DQ20 set_property PACKAGE_PIN L19 get_ports DDR4_C3_DQ21 set_property IOSTANDARD POD12_DCI get_ports DDR4_C3_DQ21 set_property PAC...

Page 66: ...get_ports DDR4_C3_DQ49 set_property PACKAGE_PIN E18 get_ports DDR4_C3_DQ50 set_property IOSTANDARD POD12_DCI get_ports DDR4_C3_DQ50 set_property PACKAGE_PIN E20 get_ports DDR4_C3_DQ51 set_property IO...

Page 67: ...property IOSTANDARD DIFF_POD12 get_ports DDR4_C3_DQS_T3 set_property PACKAGE_PIN A24 get_ports DDR4_C3_DQS_C4 set_property IOSTANDARD DIFF_POD12 get_ports DDR4_C3_DQS_C4 set_property PACKAGE_PIN A25 g...

Page 68: ...set_property IOSTANDARD DIFF_POD12 get_ports DDR4_C3_DQS_C17 set_property PACKAGE_PIN T13 get_ports DDR4_C3_DQS_T17 set_property IOSTANDARD DIFF_POD12 get_ports DDR4_C3_DQS_T17 DDR4 RESET GATING set_p...

Page 69: ..._property PACKAGE_PIN AM19 get_ports SW_DP1 set_property IOSTANDARD LVCMOS12 get_ports SW_DP1 set_property PACKAGE_PIN AL19 get_ports SW_DP2 set_property IOSTANDARD LVCMOS12 get_ports SW_DP2 set_prope...

Page 70: ..._TXD_MSP FPGA TO MSP432 U19 4 WIRE GPIO CHANNEL set_property PACKAGE_PIN AR20 get_ports GPIO_MSP0 set_property IOSTANDARD LVCMOS12 get_ports GPIO_MSP0 set_property PACKAGE_PIN AM20 get_ports GPIO_MSP1...

Page 71: ...requirements for the PC Test Environment VCU1525 Board Master Answer Record 69844 Declaration of Conformity The Virtex UltraScale VCU1525 Declaration of Conformity is TBD For Technical Support open a...

Page 72: ...take adequate measures Safety IEC 60950 1 2005 Information technology equipment Safety Part 1 General requirements EN 60950 1 2006 Information technology equipment Safety Part 1 General requirements M...

Page 73: ...Xilinx documents videos and support resources which you can filter and search to find information To open the Xilinx Documentation Navigator DocNav From the Vivado IDE select Help Documentation and Tu...

Page 74: ...Micron Technology www micron com MTA18ASF2G72PZ 2G3B1IG MT25QU01GBB8E12 0SIT 5 Samsung Electronics www samsung com M393A2K40BB1 CRC 6 Future Technology Devices International Ltd www ftdichip com FT42...

Page 75: ...dify distribute or publicly display the Materials without prior written consent Certain products are subject to the terms and conditions of Xilinx s limited warranty please refer to Xilinx s Terms of...

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