VCU1525 Acceleration Platform User Guide
68
UG1268 (v1.0) November 13, 2017
Appendix A:
Master Constraints File Listing
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T11];
set_property PACKAGE_PIN M17 [get_ports DDR4_C3_DQS_C12];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C12];
set_property PACKAGE_PIN N17 [get_ports DDR4_C3_DQS_T12];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T12];
set_property PACKAGE_PIN D23 [get_ports DDR4_C3_DQS_C13];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C13];
set_property PACKAGE_PIN D24 [get_ports DDR4_C3_DQS_T13];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T13];
set_property PACKAGE_PIN A19 [get_ports DDR4_C3_DQS_C14];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C14];
set_property PACKAGE_PIN B19 [get_ports DDR4_C3_DQS_T14];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T14];
set_property PACKAGE_PIN G19 [get_ports DDR4_C3_DQS_C15];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C15];
set_property PACKAGE_PIN H19 [get_ports DDR4_C3_DQS_T15];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T15];
set_property PACKAGE_PIN H22 [get_ports DDR4_C3_DQS_C16];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C16];
set_property PACKAGE_PIN H23 [get_ports DDR4_C3_DQS_T16];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T16];
set_property PACKAGE_PIN R13 [get_ports DDR4_C3_DQS_C17];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_C17];
set_property PACKAGE_PIN T13 [get_ports DDR4_C3_DQS_T17];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C3_DQS_T17];
# DDR4 RESET GATING
set_property PACKAGE_PIN AU21 [get_ports DDR4_RESET_GATE];
set_property IOSTANDARD LVCMOS12 DRIVE 4 [get_ports DDR4_RESET_GATE];
#QSPI0 WIRED TO FPGA U13 BANK0
#Other net PACKAGE_PIN AG12 SPI0_CS_B
#Other net PACKAGE_PIN AH12 SPI0_DQ0
#Other net PACKAGE_PIN AK12 SPI0_DQ1
#Other net PACKAGE_PIN AE12 SPI0_WP# (DQ2)
#Other net PACKAGE_PIN AJ12 SPI0_HOLD_B (DQ3)
#Other net PACKAGE_PIN AK13 FPGA_CCLK
# QSFP0
set_property PACKAGE_PIN AT20 [get_ports QSFP0_FS0];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_FS0];
set_property PACKAGE_PIN AU22 [get_ports QSFP0_FS1];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_FS1];
set_property PACKAGE_PIN BE21 [get_ports QSFP0_INTL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_INTL_LS];
set_property PACKAGE_PIN BD18 [get_ports QSFP0_LPMODE_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_LPMODE_LS];
set_property PACKAGE_PIN BE20 [get_ports QSFP0_MODPRSL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_MODPRSL_LS];
set_property PACKAGE_PIN BE16 [get_ports QSFP0_MODSKLL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_MODSKLL_LS];
set_property PACKAGE_PIN AT22 [get_ports QSFP0_REFCLK_RESET];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_REFCLK_RESET];
set_property PACKAGE_PIN BE17 [get_ports QSFP0_RESETL_LS];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP0_RESETL_LS];
# QSFP1
set_property PACKAGE_PIN AR22 [get_ports QSFP1_FS0];
set_property IOSTANDARD LVCMOS12 [get_ports QSFP1_FS0];
