VCU1525 Acceleration Platform User Guide
27
UG1268 (v1.0) November 13, 2017
Chapter 3:
Board Component Descriptions
QSFP1 Clock
[
, callout 11]
The QSFP1 clock source is a Silicon Labs SI5335A quad clock generator/buffer (U12).
• Clock generator: Silicon Labs SI5335A-B06201-GM
°
Frequency Plan: FS1, FS0 = 01
°
Input Type: crystal, input frequency 25MHz
°
Device Operating Mode: Clock Generator Loop bandwidth 1.6MHz
°
CLK0A/0B: 300MHz 1.8V LVDS
°
CLK1A/1B: 156.25MHz 1.8V LVDS
- CLK2A/2B: 90MHz 1.8V CMOS (output on A only)
- CLK3A/3B: 33.333MHz 1.8V CMOS (output on A only)
• Low phase jitter of 0.7 ps RMS
One output of the SI5335A U12 is used:
• CLK0A/B: are not used.
• CLK1A/B: The QSFP1_CLOCK_P/N clock is an AC-coupled LVDS 156.25 MHz clock wired
to QSFP1 interface GTY bank 230 MGTREFCLK1P/N input pins P11 and P10.
• CLK2A: is not used.
• CLK3A is not used.
• The FPGA connections for each clock are listed in
