
VCU1525 Acceleration Platform User Guide
52
UG1268 (v1.0) November 13, 2017
Appendix A:
Master Constraints File Listing
set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ67];
set_property PACKAGE_PIN BF37 [get_ports DDR4_C0_DQ68];
set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ68];
set_property PACKAGE_PIN BE37 [get_ports DDR4_C0_DQ69];
set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ69];
set_property PACKAGE_PIN BE40 [get_ports DDR4_C0_DQ70];
set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ70];
set_property PACKAGE_PIN BF41 [get_ports DDR4_C0_DQ71];
set_property IOSTANDARD POD12_DCI [get_ports DDR4_C0_DQ71];
set_property PACKAGE_PIN BB30 [get_ports DDR4_C0_DQS_C0];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C0];
set_property PACKAGE_PIN BA30 [get_ports DDR4_C0_DQS_T0];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T0];
set_property PACKAGE_PIN BD29 [get_ports DDR4_C0_DQS_C1];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C1];
set_property PACKAGE_PIN BD28 [get_ports DDR4_C0_DQS_T1];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T1];
set_property PACKAGE_PIN BB36 [get_ports DDR4_C0_DQS_C2];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C2];
set_property PACKAGE_PIN BB35 [get_ports DDR4_C0_DQS_T2];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T2];
set_property PACKAGE_PIN AW33 [get_ports DDR4_C0_DQS_C3];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C3];
set_property PACKAGE_PIN AV33 [get_ports DDR4_C0_DQS_T3];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T3];
set_property PACKAGE_PIN AM32 [get_ports DDR4_C0_DQS_C4];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C4];
set_property PACKAGE_PIN AM31 [get_ports DDR4_C0_DQS_T4];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T4];
set_property PACKAGE_PIN AL29 [get_ports DDR4_C0_DQS_C5];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C5];
set_property PACKAGE_PIN AL28 [get_ports DDR4_C0_DQS_T5];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T5];
set_property PACKAGE_PIN AU30 [get_ports DDR4_C0_DQS_C6];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C6];
set_property PACKAGE_PIN AU29 [get_ports DDR4_C0_DQS_T6];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T6];
set_property PACKAGE_PIN BE36 [get_ports DDR4_C0_DQS_C7];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C7];
set_property PACKAGE_PIN BE35 [get_ports DDR4_C0_DQS_T7];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T7];
set_property PACKAGE_PIN BF38 [get_ports DDR4_C0_DQS_C8];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C8];
set_property PACKAGE_PIN BE38 [get_ports DDR4_C0_DQS_T8];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T8];
set_property PACKAGE_PIN BC26 [get_ports DDR4_C0_DQS_C9];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C9];
set_property PACKAGE_PIN BB26 [get_ports DDR4_C0_DQS_T9];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T9];
set_property PACKAGE_PIN BE26 [get_ports DDR4_C0_DQS_C10];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C10];
set_property PACKAGE_PIN BD26 [get_ports DDR4_C0_DQS_T10];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T10];
set_property PACKAGE_PIN BD31 [get_ports DDR4_C0_DQS_C11];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C11];
set_property PACKAGE_PIN BC31 [get_ports DDR4_C0_DQS_T11];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_T11];
set_property PACKAGE_PIN BA33 [get_ports DDR4_C0_DQS_C12];
set_property IOSTANDARD DIFF_POD12 [get_ports DDR4_C0_DQS_C12];