Xilinx VCU1525, User Manual

Page: 11 / 75

VCU1525 Acceleration Platform User Guide 11
UG1268 (v1.0) November 13, 2017 www.xilinx.com
Chapter 2: Board Setup and Configuration
CAUTION!
The VCU1525 board can be damaged by electrostatic discharge (ESD). Follow standard ESD
prevention measures when handling the board.
Table 2-1: VCU1525 Board Component Descriptions
Number Ref Des
Feature
(Link)
Notes
Schematic
Page
1 U13 Virtex Ult
XCVU9P-L2FSGD2104E FPGA
XCVU9P-L2FSGD2104E —
2 J14 C0 DDR4 72-bit DIMM memory
(16 GB)
(
DDR4 DIMM Memory )
Micron MTA18ASF2G72PZ-2G3B1IG 33
3 J12 C1 DDR4 72-bit DIMM memory
(16 GB)
(
DDR4 DIMM Memory )
Micron MTA18ASF2G72PZ-2G3B1IG 34
4 J5 C2 DDR4 72-bit DIMM memory
(16 GB)
(
DDR4 DIMM Memory )
Micron MTA18ASF2G72PZ-2G3B1IG 35
5 J2 C3 DDR4 72-bit DIMM memory
(16 GB)
(
DDR4 DIMM Memory )
Micron MTA18ASF2G72PZ-2G3B1IG 36
6 U17 Quad SPI Flash Memory (1Gb total) Micron MT25QU01GBBA8E12-0SIT 12
7 U27, J13 USB JTAG bridge w/ USB Micro-AB
connector
(
FT4232HQ USB-UART Interface )
FTDI FT4232HQ-REEL
HIROSE ZX62D-AB-5P8 31
8 J1 SMBUS 2X5 1.27mm pitch connector
(
Monitoring Voltage and Current )
SAMTEC FTSH-105-01-F-D-K 16
9 J3 BMC CTLR. JTAG 2 X 5 1.27 mm pitch
connector
(
Figure 3-17 U19 MSP432 I2C
Connectivity )
SAMTEC FTSH-105-01-F-D-K 24
10 U9 SYSCLK_300 300MHz, QSFP0_CLOCK
156.25MHz, 1.8V LVDS
(
System Clock and QSFP0 Clock )
SI5335A-B06201-GM 23
11 U12 QSFP1_CLOCK 156.25MHz, 1.8V
LVDS ( QSFP1 Clock )
SI5335A-B06201-GM 27
12 U14, U43 USER_SI570_CLOCK, 156.25MHz,
3.3V LVDS
+1 to 4 clock buffer
(
Programmable MGT and User
Clock )
Silicon Labs SI570BAB000544DG
Silicon Labs SI53340-B-GM 23
13 J7 QSFP0 (40Gb Ethernet) ( 28 Gb/s
QSFP+ Module Connectors )
AMPHENOL FS1-Z38-20Z6-60 23
14 J9 QSFP1 (40Gb Ethernet) ( 28 Gb/s
QSFP+ Module Connectors )
AMPHENOL FS1-Z38-20Z6-60 27
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