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7 Series FPGAs SelectIO Resources User Guide

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UG471 (v1.10) May 8, 2018

ILOGIC Resources

ILOGIC Timing Models

This section describes the timing associated with the various resources within the ILOGIC
block.

ILOGIC Timing Characteristics

Figure 2-9

illustrates ILOGIC register timing. When IDELAY is used, T

IDOCK

is replaced by

IDOCKD

Clock Event 1

•

At time T

ICE1CK

before Clock Event 1, the input clock enable signal becomes

valid-high at the CE1 input of the input register, enabling the input register for
incoming data.

•

At time T

IDOCK

before Clock Event 1, the input signal becomes valid-high at the D

input of the input register and is reflected on the Q1 output of the input register at
time T

ICKQ

after Clock Event 1.

Clock Event 4

•

At time T

ISRCK

before Clock Event 4, the S/R signal (configured as synchronous reset

in this case) becomes valid-high resetting the input register and reflected at the Q1
output of the IOB at time T

ICKQ

after Clock Event 4.

ILOGIC Timing Characteristics, DDR

Figure 2-10

illustrates the ILOGIC in IDDR mode timing characteristics. When IDELAY is

used, T

IDOCK

is replaced by T

IDOCKD

. The example shown uses IDDR in

OPPOSITE_EDGE mode. For other modes, add the appropriate latencies as shown in

Figure 2-7, page 111

X-Ref Target - Figure 2-9

Figure 2-9:

ILOGIC Input Register Timing Characteristics

CLK

CE1

S/R

ICKQ

IDOCK

ICE1CK

ISRCK

ug471_c2_07_081215

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Summary of Contents for SelectIO 7 Series

Page 1: ...7 Series FPGAs SelectIO Resources User Guide UG471 v1 10 May 8 2018 ...

Page 2: ...CONSISTENT WITH THE ISO 26262 AUTOMOTIVE SAFETY STANDARD SAFETY DESIGN CUSTOMER SHALL PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE PRODUCTS THOROUGHLY TEST SUCH SYSTEMS FOR SAFETY PURPOSES USE OF PRODUCTS IN A SAFETY APPLICATION WITHOUT A SAFETY DESIGN IS FULLY AT THE RISK OF CUSTOMER SUBJECT ONLY TO APPLICABLE LAWS AND REGULATIONS GOVERNING LIMITATIONS ON PRODUCT LIABILITY Copyrigh...

Page 3: ...ontrol Output TFB and Reset Input RST page 164 Updated OSERDESE2 Clocking Methods and OSERDESE2 Width Expansion Updated latencies in Table 3 11 Added IO_FIFO Overview Updated Resetting the IO_FIFO Added Appendix A Termination Options for SSO Noise Analysis 10 31 2012 1 3 Removed XC7V1500T from third bullet after Figure 1 7 05 13 2014 1 4 Updated VCCO Added item to bulleted list after Figure 1 7 Up...

Page 4: ...e 1 58 Figure 1 60 and Figure 1 62 Added note 2 to Table 1 55 Added Vivado Design Suite to Pin Planning to Mitigate SSO Sensitivity Updated description of clock input C in IDELAY Ports and ODELAY Ports Replaced SR with S R in Figure 2 17 Figure 2 20 and Table 2 10 09 18 2015 1 6 Replaced SR with S R throughout Added note about set and reset pins to Table 2 1 and Table 2 10 In RDY Ready updated sen...

Page 5: ...I Requirements for Some Banks 22 DCI Cascading 22 Controlled Impedance Driver Source Termination 25 Controlled Impedance Driver with Half Impedance Source Termination 25 Split Termination DCI Thevenin Equivalent Termination to VCCO 2 26 VRN VRP External Resistance Design Migration Guidelines 27 DCI and 3 state DCI T_DCI 28 DCI in 7 Series FPGAs I O Standards 29 DCI Usage Examples 31 Uncalibrated S...

Page 6: ...STL_ I and HSTL_ I_18 60 HSTL_I_12 60 HSTL_ I_DCI and HSTL_ I_DCI_18 60 HSTL_ II and HSTL_ II_18 60 HSTL_ II_DCI and HSTL_ II_DCI_18 61 HSTL_ II_T_DCI and HSTL_ II_T_DCI_18 61 DIFF_HSTL_I and DIFF_HSTL_I_18 61 DIFF_HSTL_I_DCI and DIFF_HSTL_I_DCI_18 61 DIFF_HSTL_ II and DIFF_HSTL_II_18 61 DIFF_HSTL_II_DCI and DIFF_HSTL_II_DCI_18 62 DIFF_HSTL_II_T_DCI and DIFF_HSTL_II_T_DCI_18 62 HSTL Class I 1 2V 1...

Page 7: ...VDS Bus LVDS 96 Rules for Combining I O Standards in the Same Bank 97 Simultaneous Switching Outputs 104 Pin Planning to Mitigate SSO Sensitivity 104 Chapter 2 SelectIO Logic Resources Introduction 105 ILOGIC Resources 106 Combinatorial Input Path 109 Input DDR Overview IDDR 109 OPPOSITE_EDGE Mode 109 SAME_EDGE Mode 110 SAME_EDGE_PIPELINED Mode 110 Input DDR Resources IDDR 111 IDDR VHDL and Verilo...

Page 8: ... 145 ISERDESE2 Ports 146 Registered Outputs Q1 to Q8 146 Combinatorial Output O 147 Bitslip Operation BITSLIP 147 Clock Enable Inputs CE1 and CE2 147 High Speed Clock Input CLK 148 High Speed Clock Input CLKB 148 Divided Clock Input CLKDIV 148 Serial Input Data from IOB D 148 Serial Input Data from IDELAYE2 DDLY 149 Serial Input Data from OSERDESE2 OFB 149 High Speed Clock for Strobe Based Memory ...

Page 9: ...t Data Clock Enable OCE 164 3 state Signal Clock Enable TCE 164 Parallel 3 state Inputs T1 to T4 164 OSERDESE2 Attributes 165 DATA_RATE_OQ Attribute 165 DATA_RATE_TQ Attribute 165 DATA_WIDTH Attribute 166 SERDES_MODE Attribute 166 TRISTATE_WIDTH Attribute 166 OSERDESE2 Clocking Methods 166 OSERDESE2 Width Expansion 167 Guidelines for Expanding the Parallel to Serial Converter Bit Width 168 Output ...

Page 10: ...10 www xilinx com 7 Series FPGAs SelectIO Resources User Guide UG471 v1 10 May 8 2018 Send Feedback ...

Page 11: ...tex 7 family is optimized for highest system performance and capacity This guide serves as a technical reference describing the 7 series FPGAs SelectIO resources This 7 series FPGAs SelectIO resources user guide part of an overall set of documentation on the 7 series FPGAs is available on the Xilinx website at www xilinx com documentation Guide Contents This manual contains the following chapters ...

Page 12: ...12 www xilinx com 7 Series FPGAs SelectIO Resources User Guide UG471 v1 10 May 8 2018 Preface About This Guide Send Feedback ...

Page 13: ...ned to support a wider range of I O standards with voltages up to 3 3V Table 1 1 highlights the features supported in the HP and HR I O banks Refer to Table 1 1 for help when making initial decisions on I O banks for a particular design s requirements See the specific device family data sheet for details on the performance and other electrical requirements of the HP and HR I O banks The 7 series F...

Page 14: ... shows among other features which I O standards support the SLEW attribute The 7 series FPGA DCI calibration circuit has improved the accuracy of the internal termination resistance As a result the selection of values for the external precision resistors is different for the split termination DCI standards Specifically the external resistors are now chosen to be double the target Thevenin equivale...

Page 15: ...ifferential Single ended I O standards e g LVCMOS LVTTL HSTL PCI and SSTL Differential I O standards e g LVDS Mini_LVDS RSDS PPDS BLVDS and differential HSTL and SSTL Figure 1 1 shows the single ended only HP I O block IOB and its connections to the internal logic and the device pad Figure 1 2 shows the regular HP IOB Figure 1 3 shows the single ended only HR IOB Figure 1 4 shows the regular HR IO...

Page 16: ...Diagram X Ref Target Figure 1 3 Figure 1 3 Single Ended Only HR IOB Diagram X Ref Target Figure 1 4 Figure 1 4 Regular HR IOB Diagram UG471_c1_04_010711 PAD O T I DIFFO_OUT O_OUT PADOUT DCITERMDISABLE DIFFI_IN IBUFDISABLE UG471_c1_05 _011010 PAD O T I PADOUT DIFFI_IN IBUFDISABLE UG471_c1_06_011110 PAD O T I DIFFO_OUT O_OUT PADOUT DIFFI_IN IBUFDISABLE Send Feedback ...

Page 17: ...ut In the 7 Series FPGAs Overview the total number of available I O banks is listed by device type For example the XC7K325T has 10 usable I O banks Figure 1 5 is an example of a columnar floorplan showing the XC7K325T I O banks UG475 7 Series FPGAs Packaging and Pinout Specifications includes information on the I O banks for each device package combination X Ref Target Figure 1 5 Figure 1 5 7 Seri...

Page 18: ...aints page 46 VCCAUX The global auxiliary VCCAUX supply rail is primarily used for providing power to the various block feature s interconnect logic inside the 7 series FPGAs In the I O banks VCCAUX is also used to power input buffer circuits for some of the I O standards These include all of the single ended I O standards at or below 1 8V and also some of the 2 5V standards HR I O banks only Addi...

Page 19: ...multi function or multi purpose pins that can also be used for configuration but then convert to normal I O pins after configuration is complete Additionally in SSI devices pins in banks 11 12 17 18 20 and 21 have restrictions during configuration similar to multi function pins However pins in these banks do not have any configuration functions In devices where bank 14 and or bank 15 are HR banks ...

Page 20: ...e VRN multi function pin to a precision resistor tied to the VCCO rail for the same bank 3 Connect the VRP multi function pin to a precision resistor tied to ground The following sections discuss how to determine the precision resistor values for VRN and VRP for the different I O standards Only one set of VRN and VRP resistors is used for each bank so all DCI standards within each bank must be abl...

Page 21: ...rformed the first match calibration to the external reference resistors This option is also sometimes referred to as DCI match For more information about the Match_cycle option refer to the Configuration Details chapter in UG470 7 Series FPGAs Configuration User Guide For information on how to invoke the option in a design and to set it to a specific startup cycle refer to the Match_cycle option i...

Page 22: ...was set to AsRequired after those pins become normal I O pins there would be an indeterministic delay between the end of configuration and when the DCI calibration algorithm updated those pins DCI settings If DCIRESET was not used and DCIUpdateMode was set to Quiet these pins would never have their DCI values set In that case the Controlled Impedance DCI I O standards such as LVDCI_18 would behave...

Page 23: ...ading support over multiple I O banks Bank B is the master I O bank and Banks A and C are considered slave I O banks X Ref Target Figure 1 7 Figure 1 7 DCI Cascading Supported Over Multiple I O Banks UG471_c1_09_011811 DCI VRN VRP Bank A Bank B Bank C To Local Bank To Local Bank To Local Bank To Banks Above When Cascaded To Banks Below When Cascaded Send Feedback ...

Page 24: ...ter and slave I O banks must have the same VCCO and VREF if applicable voltage I O banks in the same HP I O column that are not using DCI pass through banks do not have to comply with the VCCO and VREF voltage rules for combining DCI settings DCI I O banking compatibility rules must be satisfied across all master and slave banks for example only one DCI I O standard using single termination type i...

Page 25: ... the use of an external source termination resistor The impedance is set by the external reference resistors with resistance equal to the trace impedance The DCI I O standards supporting the controlled impedance driver are LVDCI_15 LVDCI_18 HSLVDCI_15 HSLVDCI_18 HSUL_12_DCI and DIFF_HSUL_12_DCI Figure 1 8 illustrates a controlled impedance driver in a 7 series device Controlled Impedance Driver wi...

Page 26: ...l termination circuit of 50Ω to VCCO 2 would require 100Ω external precision resistors at the VRN and VRP pins The DCI input standards supporting split termination are shown in Table 1 2 X Ref Target Figure 1 10 Figure 1 10 Input Termination to VCCO 2 without DCI R UG471_c1_12_011811 VCCO 2 VREF IOB Z0 7 Series FPGA Table 1 2 All DCI I O Standards Supporting Split Termination DCI HSTL_I_DCI DIFF_H...

Page 27: ...O 2 requires 100Ω external resistors on the VRN and VRP pins This is particularly important to consider when choosing the VRN and VRP values to be used in the same I O bank or multiple cascaded DCI banks for both controlled impedance DCI and split termination DCI standards In a Virtex 6 FPGA design with a 50Ω target controlled impedance driver for an LVDCI_18 output and a 50Ω target split terminat...

Page 28: ...re 1 12 illustrates a driver with split termination inside a 7 series device When the split termination is present while driving DCI only controls the impedance of the termination but not the driver However many applications can benefit from having the split termination resistors turned off whenever the pin is driving The 3 state DCI T_DCI standards were designed to meet this requirement by turnin...

Page 29: ...rsions of the HSTL and SSTL I O standards only have the split termination DCI resistors present on inputs not outputs Bidirectional pin assignments are not allowed for these standards Table 1 4 I O Standards with Split Termination DCI Only When 3 Stated HSTL_II_T_DCI SSTL18_II_T_DCI DIFF_SSTL18_II_T_DCI HSTL_II_T_DCI_18 SSTL15_T_DCI DIFF_SSTL15_T_DCI DIFF_HSTL_II__T_DCI SSTL135_T_DCI DIFF_SSTL135_...

Page 30: ...ernal reference resistors to the VRP VRN pins When these DCI based I O standards are the only ones in a bank the VRP and VRN pins in that bank can be used as general purpose I O DCI inputs that do not require reference resistors on VRP VRN are shown in Table 1 6 4 The value of the external reference resistors should be selected to give the desired output driver impedance or split termination imped...

Page 31: ..._c1_15_011811 Conventional DCI Transmit Conventional Receive Conventional Transmit DCI Receive DCI Transmit DCI Receive Bidirectional Reference Resistor Recommended Z0 VRN VRP 2R 2Z0 50Ω VRN VRP 2R 2Z0 50Ω HSTL_I HSTL_II N A Z0 R R 2R 2R 2R 2R Z0 Z0 Z0 Z0 Z0 Z0 Z0 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Ser...

Page 32: ...it DCI Receive Bidirectional Reference Resistor Recommended Z0 VRN VRP 2R 2Z0 50Ω VRN VRP 2R 2Z0 50Ω N A Z0 R R 2R 2R 2R 2R Z0 Z0 Z0 Z0 Z0 Z0 Z0 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI 7 Series FPGA HP Bank DCI Z0 2R 2R 2R 2R VCCO 2...

Page 33: ... process or voltage variations This option has target Thevenin equivalent resistance values of 40Ω 50Ω and 60Ω Another difference from the DCI termination is how this uncalibrated termination is invoked in a design While the 3 state split termination DCI option is invoked by assigning the T_DCI I O standards to I O pins in HP I O banks the uncalibrated split termination option is invoked by assign...

Page 34: ...ts IBUFDS_DIFF_OUT_IBUFDISABLE differential input buffer with complementary outputs and buffer disable IBUFDS_DIFF_OUT_INTERMDISABLE differential input buffer with complementary outputs buffer disable and IN_TERM disable IBUFDS_IBUFDISABLE differential input buffer with buffer disable control IBUFDS_INTERMDISABLE differential input buffer with buffer disable and IN_TERM disable IBUFGDS differentia...

Page 35: ...ed as an additional power saving feature for periods when the input is not used The IBUF_IBUFDISABLE primitive can disable the input buffer and force the O output to the fabric to a logic High when the USE_IBUFDISABLE attribute is set to TRUE and the IBUFDISABLE signal is asserted High If USE_IBUFDISABLE is set to FALSE this input is ignored and should be tied to ground This feature can be used to...

Page 36: ...ow The IBUF_INTERMDISABLE primitive further allows the termination legs to be disabled whenever the INTERMDISABLE signal is asserted High These features can be combined to reduce power whenever the input is idle Input buffers that use the VREF power rail such as SSTL and HSTL benefit the most from the IBUFDISABLE signal being set to TRUE because they tend to have higher static power consumption th...

Page 37: ...r and force both the O and OB outputs to the fabric high when the USE_IBUFDISABLE attribute is set to TRUE and the IBUFDISABLE signal is asserted High If USE_IBUFDISABLE is set to FALSE this input is ignored and should be tied to ground This feature can be used to reduce power whenever the I O is idle IBUFDS_IBUFDISABLE The IBUFDS_IBUFDISABLE primitive shown in Figure 1 21 is a differential input ...

Page 38: ...IN_TERM for more details on this feature The IBUFDS_INTERMDISABLE primitive can disable the input buffer and force the O output to the fabric High when the USE_IBUFDISABLE attribute is set to TRUE and the IBUFDISABLE signal is asserted High If USE_IBUFDISABLE is set to FALSE the IBUFDISABLE input is ignored and should be tied to ground If the I O is using the optional uncalibrated split terminatio...

Page 39: ... the INTERMDISABLE signal is asserted High These features can both be combined to reduce power whenever the input is idle IOBUF The IOBUF primitive is needed when bidirectional signals require both an input buffer and a 3 state output buffer with an active High 3 state T pin Figure 1 24 shows a generic 7 series FPGA IOBUF A logic High on the T pin disables the output buffer IOBUF_DCIEN The IOBUF_D...

Page 40: ...further allows the termination legs to be disabled whenever the DCITERMDISABLE signal is asserted High These features can be combined to reduce power whenever the input is idle for a period of time IOBUF_INTERMDISABLE The IOBUF_INTERMDISABLE primitive shown in Figure 1 26 is available in the HR I O banks It has an IBUFDISABLE port that can be used to disable the input buffer during periods that th...

Page 41: ... features can be combined to reduce power whenever the input is idle for a period of time IOBUFDS Figure 1 27 shows the differential input output buffer primitive A logic High on the T pin disables the output buffer IOBUFDS_DCIEN The IOBUFDS_DCIEN primitive shown in Figure 1 28 is available in the HP I O banks It has a IBUFDISABLE port that can be used to disable the input buffer during periods th...

Page 42: ...signals With 3 state DCI I O standards the DCI termination legs turn off whenever the driver is active The IOBUFDS_DCIEN primitive further allows the termination legs to be disabled whenever the DCITERMDISABLE signal is asserted High These features can be combined to reduce power whenever the input is idle for a period of time IOBUFDS_DIFF_OUT Figure 1 29 shows the differential input output buffer...

Page 43: ...n disable the input buffer and force both the O and OB outputs to the fabric High when the USE_IBUFDISABLE attribute is set to TRUE and the IBUFDISABLE signal is asserted High If USE_IBUFDISABLE is set to FALSE this input is ignored and should be tied to ground If the I O is using the X Ref Target Figure 1 29 Figure 1 29 Differential Input Output Buffer Primitive With Complementary Outputs for the...

Page 44: ... feature The IOBUFDS_DIFF_OUT_INTERMDISABLE primitive can disable the input buffer and force both the O and OB outputs to the fabric High when the USE_IBUFDISABLE attribute is set to TRUE and the IBUFDISABLE signal is asserted High If USE_IBUFDISABLE is set to FALSE this input is ignored and should be tied to ground If the I O is using the optional uncalibrated split termination feature IN_TERM th...

Page 45: ...isabled whenever the driver is active T is low This primitive further allows the termination legs to be disabled whenever the INTERMDISABLE signal is asserted High These features can be combined to reduce power whenever the input is idle for a period of time OBUF An output buffer OBUF must be used to drive signals from 7 series devices to external output pads A generic 7 series FPGA OBUF primitive...

Page 46: ...e constraints and attributes as well as others see UG625 Constraints Guide for the ISE tools or UG912 Vivado Design Suite Properties Reference Guide DCI_CASCADE Constraint The DCI_CASCADE constraint identifies a DCI master bank and its corresponding slave banks See DCI Cascading page 22 for more information X Ref Target Figure 1 34 Figure 1 34 Differential Output Buffer Primitive OBUFDS ug471_c1_2...

Page 47: ...NAL_PORT_IDENTIFIER Example INST MY_IO LOC R7 IOSTANDARD Attribute The IOSTANDARD attribute is available to choose the values for an I O standard for all I O buffers The supported I O standards are listed in the specific 7 series FPGAs data sheets however Table 1 56 lists the IOSTANDARD support by bank type HR HP or both The IOSTANDARD attribute uses the following syntax in the UCF file INST I O_B...

Page 48: ...ired slew rate can be specified with the SLEW attribute It might be important to specify FAST slew rate for high performance applications such as high frequency memory interfaces However faster slew rates can also lead to reflections or increased noise issues if not properly designed such as with terminations transmission line impedance continuity and cross coupling The allowed values for the SLEW...

Page 49: ...tial Termination Attribute The differential termination DIFF_TERM attribute supports the differential I O standards when used as inputs It is used to turn the built in 100Ω differential termination on or off The on chip input differential termination in 7 series devices provides major advantages over using a discrete resistor by removing the stub at the receiver completely and therefore greatly im...

Page 50: ...aint INTERNAL_VREF_BANK14 0 75 Example 2 INTERNAL_VREF for Bank 15 using HSTL_II_18 1 8V which requires a 0 9V reference voltage uses the following constraint INTERNAL_VREF_BANK15 0 90 The rules for using INTERNAL_VREF are One value of VREF can be set for the bank INTERNAL_VREF can only be set to the nominal reference voltage value of a given I O standard Valid settings of INTERNAL_VREF are 0 60 0...

Page 51: ... Standards and Terminations The following sections provide an overview of the I O standards and options supported by all 7 series devices While most 7 series FPGA I O supported standards specify a range of allowed voltages this chapter records typical voltage values only Detailed information on each specification can be found on the Electronic Industry Alliance JEDEC web site at http www jedec org...

Page 52: ...ectIO Resources Figure 1 37 shows unidirectional terminated topologies X Ref Target Figure 1 37 Figure 1 37 LVTTL Unidirectional Termination Z0 IOB IOB LVTTL LVTTL Z0 IOB IOB LVTTL LVTTL Z0 IOB IOB LVTTL LVTTL ug471_c1_27_011811 VTT Note VTT is any voltage from 0V to VCCO RP Z0 RS Z0 RD Send Feedback ...

Page 53: ... LVTTL I O standard This standard is only available in the HR I O banks X Ref Target Figure 1 38 Figure 1 38 LVTTL Bidirectional Termination Table 1 10 Allowed Attributes for the LVTTL I O Standards Attributes Primitives IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD LVTTL LVTTL DRIVE N A 4 8 12 default 16 24 SLEW N A FAST SLOW Z0 IOB IOB LVTTL Z0 IOB IOB LVTTL LVTTL VTT Note VTT is any voltage from 0V to...

Page 54: ...circuits illustrating both unidirectional and bidirectional LVCMOS termination techniques are shown in Figure 1 39 and Figure 1 40 These two diagrams show examples of source series and parallel terminated topologies Figure 1 39 shows unidirectional terminated topologies Table 1 11 Available I O Bank Type HR HP Available Available X Ref Target Figure 1 39 Figure 1 39 LVCMOS Unidirectional Terminati...

Page 55: ...HR and HP I O banks X Ref Target Figure 1 40 Figure 1 40 LVCMOS Bidirectional Termination Table 1 12 Allowed Attributes for the LVCMOS33 and LVCMOS25 I O Standards Attributes Primitives IBUF IBUFG OBUF OBUFT IOBUF IOSTANDARD LVCMOS33 LVCMOS25 LVCMOS33 LVCMOS25 DRIVE N A 4 8 12 16 SLEW N A FAST SLOW Table 1 13 Allowed Attributes for the LVCMOS18 I O Standard Attributes Primitives IBUF IBUFG OBUF OB...

Page 56: ...e output driver to provide series termination without external source termination resistors The impedance is set by the common external reference resistors with resistance equal to the trace characteristic impedance Z0 Sample circuits illustrating both unidirectional and bidirectional topologies for a controlled impedance driver are shown in Figure 1 41 and Figure 1 42 The DCI I O standards suppor...

Page 57: ...r with half impedance are LVDCI_DV2_15 and LVDCI_DV2_18 Figure 1 43 and Figure 1 44 illustrate a controlled driver with half impedance unidirectional topologies To match the drive impedance to Z0 when using a driver with half impedance the reference resistor R must be twice Z0 X Ref Target Figure 1 41 Figure 1 41 Unidirectional Controlled Impedance Driver Topology X Ref Target Figure 1 42 Figure 1...

Page 58: ... resistors it is indicated by the addition of DV2 to the attribute name X Ref Target Figure 1 43 Figure 1 43 Unidirectional Controlled Impedance Driver with Half Impedance Topology X Ref Target Figure 1 44 Figure 1 44 Bidirectional Controlled Impedance Driver with Half Impedance Topology Z0 IOB IOB LVDCI_DV2 LVDCI_DV2 ug471_c1_33_011811 R0 RVRN RVRP Z0 Z0 IOB IOB LVDCI_DV2 LVDCI_DV2 ug471_c1_34_01...

Page 59: ...uit illustrating bidirectional termination techniques for an HSLVDCI controlled impedance driver is shown in Figure 1 45 The DCI I O standards supporting a controlled impedance driver with a VREF referenced input are HSLVDCI_15 and HSLVDCI_18 For electrical specifications refer to the LVDCI VOH and VOL entries in the 7 series data sheets Table 1 18 Available I O Bank Type HR HP N A Available X Ref...

Page 60: ... support DCI versions HSTL_ I and HSTL_ I_18 HSTL_I and HSTL_ I_18 use VCCO 2 as a parallel termination voltage VTT and are intended for use in unidirectional links HSTL_I_12 HSTL_I_12 uses VCCO 2 as a parallel termination voltage VTT and is intended for use in unidirectional links HSTL_ I_DCI and HSTL_ I_DCI_18 HSTL_I_DCI and HSTL_I_DCI_18 provide on chip split thevenin termination powered from V...

Page 61: ... HSTL class I pairs complementary single ended HSTL_I type drivers with a differential receiver and are intended to be used in unidirectional links DIFF_HSTL_I_DCI and DIFF_HSTL_I_DCI_18 Differential HSTL class I pairs complementary single ended HSTL_I type drivers with a differential receiver including on chip split thevenin termination and are intended to be used in unidirectional links DIFF_HST...

Page 62: ...ferential clock and DQS signals in memory interface designs DIFF_HSTL_II_T_DCI and DIFF_HSTL_II_T_DCI_18 These standards are almost the same as the DIFF_HSTL_II_DCI and DIFF_HSTL_II_DCI_18 standards except that the termination is only present when the driver is 3 stated HSTL Class I 1 2V 1 5V or 1 8V Figure 1 46 shows a sample circuit illustrating a termination technique for HSTL class I for the 1...

Page 63: ...L_I HSTL_I_12 HSTL_I_18 HSTL_I HSTL_I_12 HSTL_I_18 ug471_c1_36_021214 VTT 0 75V for HSTL_I 0 6V for HSTL_I_12 0 9V for HSTL_I_18 RP Z0 50Ω Z0 IOB IOB HSTL_I_DCI HSTL_I_DCI_18 HSTL_I_DCI HSTL_I_DCI_18 VCCO 1 5V for HSTL_I_DCI 1 8V for HSTL_I_DCI_18 RVRN 2Z0 100Ω RVRP 2Z0 100Ω VREF 0 75V for HSTL_I 0 6V for HSTL_I_12 0 9V for HSTL_I_18 VREF 0 75V for HSTL_I_DCI 0 9V for HSTL_I_DCI_18 External Termin...

Page 64: ...rmination In a specific circuit all drivers and receivers must be at the same voltage level either 1 5V or 1 8V they are not interchangeable X Ref Target Figure 1 47 Figure 1 47 Differential HSTL Class I 1 5V or 1 8V Unidirectional Termination ug471_c1_37_011811 External Termination Z0 IOB IOB DIFF_HSTL_I DIFF_HSTL_I_18 DIFF_HSTL_I DIFF_HSTL_I_18 DIFF_HSTL_I DIFF_HSTL_I_18 Z0 VTT 0 75V for HSTL_I ...

Page 65: ...e voltage level either 1 5V or 1 8V they are not interchangeable Only HP I O banks support these DCI standards X Ref Target Figure 1 48 Figure 1 48 Differential HSTL Class I 1 5V or 1 8V DCI Unidirectional Termination ug471_c1_38_021214 IOB DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_18 DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_18 DIFF_HSTL_I_DCI DIFF_HSTL_I_DCI_18 VCCO 1 5V for DIFF_HSTL_I_DCI 1 8V for DIFF_HSTL_I_DCI...

Page 66: ...re always present independent of whether the drivers are 3 stated X Ref Target Figure 1 49 Figure 1 49 HSTL Class II 1 5V or 1 8V Unidirectional Termination Z0 IOB IOB HSTL_II HSTL_II_18 HSTL_II HSTL_II_18 ug471_c1_39_121214 VTT 0 75V for HSTL_II 0 9V for HSTL_II_18 VTT 0 75V for HSTL_II 0 9V for HSTL_II_18 RP Z0 50Ω RP Z0 50Ω Z0 IOB IOB HSTL_II_DCI HSTL_II_DCI_ 8 HSTL_II_DCI HSTL_II_DCI_ 8 VCCO 1...

Page 67: ...vers are 3 stated X Ref Target Figure 1 50 Figure 1 50 HSTL Class II 1 5V or 1 8V Bidirectional Termination Z0 IOB IOB HSTL_II HSTL_II_18 HSTL_II HSTL_II_18 HSTL_II_DCI HSTL_II_DCI_18 HSTL_II_DCI HSTL_II_DCI_18 ug471_c1_40_121214 RP Z0 50Ω RP Z0 50Ω Z0 IOB IOB VCCO 1 5V for HSTL_II_DCI 1 8V for HSTL_II_DCI_18 VCCO 1 5V for HSTL_II_DCI 1 8V for HSTL_II_DCI_18 RVRN 2Z0 100Ω RVRP 2Z0 100Ω External Te...

Page 68: ...e same voltage level either 1 5V or 1 8V they are not interchangeable X Ref Target Figure 1 51 Figure 1 51 Differential HSTL Class II 1 5V or 1 8V Unidirectional Termination ug471_c1_41_011811 External Termination Z0 IOB IOB DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II_18 Z0 50Ω VTT 0 75V for DIFF_HSTL_II 0 9V for DIFF_HSTL_II_18 VTT 0 75V for DIFF_HSTL_II 0 ...

Page 69: ...ors are always present independent of whether the drivers are 3 stated X Ref Target Figure 1 52 Figure 1 52 Differential HSTL Class II 1 5V or 1 8V DCI Unidirectional Termination ug471_c1_42_121214 IOB DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 VCCO 1 5V for DIFF_HSTL_II_DCI 1 8V for DIFF_HSTL_II_DCI_18 VCCO 1 5V for DIFF_HSTL_II_...

Page 70: ...erchangeable X Ref Target Figure 1 53 Figure 1 53 Differential HSTL Class II 1 5V or 1 8V Bidirectional Termination Z0 IOB IOB DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II_18 DIFF_HSTL_II DIFF_HSTL_II_18 External Termination 50Ω ug471_c1_43_011811 Z0 50ϖ VTT 0 75V for DIFF_HSTL_II 0 9V for DIFF_HSTL_II...

Page 71: ...tated X Ref Target Figure 1 54 Figure 1 54 Differential HSTL Class II 1 5V or 1 8V DCI Bidirectional Termination Z0 IOB IOB DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_18 VCCO 1 5V for DIFF_HSTL_II_DCI VCCO 1 8V for DIFF_HSTL...

Page 72: ... be at the same voltage level either 1 5V or 1 8V they are not interchangeable Only HP I O banks support the T_DCI standards The internal split termination resistors are only present when the output buffers are 3 stated X Ref Target Figure 1 55 Figure 1 55 HSTL_II_T_DCI 1 5V and HSTL_II_T_DCI_18 1 8V Split Thevenin Termination 3 state ug471_c1_45_021214 Z0 IOB IOB 1 0 HSTL_II_T_DCI HSTL_II_T_DCI_1...

Page 73: ...esent when the output buffers are 3 stated X Ref Target Figure 1 56 Figure 1 56 Differential HSTL Class II 1 5V or 1 8V DCI with Split Thevenin Termination 3 state Z0 IOB 0 0 1 1 IOB DIFF_HSTL_II_DCI_T DIFF_HSTL_II_DCI_T_18 DIFF_HSTL_II_DCI_T DIFF_HSTL_II_DCI_T_18 DIFF_HSTL_II_DCI_T DIFF_HSTL_II_DCI_T_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_T_18 DIFF_HSTL_II_DCI DIFF_HSTL_II_DCI_T_18 DIFF_HSTL_II_DCI...

Page 74: ...For some topologies such as short point to point interfaces the class I driver can result in reduced overshoot and better signal integrity SSTL18 class I and class II are available in both the HP and HR I O banks with the HP banks providing DCI and T_DCI options for tuned internal parallel split termination resistors The T_DCI option is only available for bidirectional signals no input only or out...

Page 75: ...le the DCI option is not available for bidirectional signals input or output only the T_DCI option is only available for bidirectional signals no input only or output only HR banks provide IN_TERM options for untuned internal parallel split termination resistors Although the optimal drive and termination scheme for any new design is determined through careful signal integrity analysis initial cons...

Page 76: ... for inputs SSTL18_I_DCI DIFF_SSTL18_I_DCI These standards are only available for unidirectional input or output signals Class I drivers can be preferred for short point to point board topologies DCI provides tuned internal parallel split termination resistors that are always present for receivers The value of both the pull up and pull down resistors mirror the resistance measured on the VRN VRP p...

Page 77: ...The termination is disabled whenever the output buffer is driving The value of both the pull up and pull down resistors mirror the resistance measured on the VRN VRP pins creating the Thevenin equivalent resistance to the VCCO 2 mid point level The differential DIFF_ versions use complementary single ended drivers for outputs and differential receivers for inputs SSTL12 SSTL12_DCI SSTL12_T_DCI DIF...

Page 78: ...12 Unidirectional Termination Z0 IOB IOB SSTL18_ I II SSTL15 _R SSTL135 _R SSTL12 SSTL18_ I II SSTL15 _R SSTL135 _R SSTL12 ug471_c1_47_121214 VTT 0 9V for SSTL18_ I II 0 75V for SSTL15 _R 0 675V for SSTL135 _R 0 6V for SSTL12 RP Z0 50Ω Z0 IOB IOB SSTL18_ I II _DCI SSTL15_DCI SSTL135_DCI SSTL12_DCI SSTL18_ I II _DCI SSTL15_DCI SSTL135_DCI SSTL12_DCI VCCO 1 8V for SSTL18_ I II _DCI 1 5V for SSTL15_D...

Page 79: ...f SSTL15 SSTL135 and SSTL12 with DCI termination The internal split termination resistors are always present on SSTL18_II_DCI independent of whether the drivers are 3 stated X Ref Target Figure 1 58 Figure 1 58 SSTL18 SSTL15 SSTL135 or SSTL12 Bidirectional Termination Z0 IOB SSTL18_II SSTL15 _R SSTL135 _R SSTL12 SSTL18_II SSTL15 _R SSTL135 _R SSTL12 ug471_c1_48_121214 VTT 0 9V for SSTL18_II 0 75V ...

Page 80: ...ble X Ref Target Figure 1 59 Figure 1 59 Differential SSTL18 SSTL15 SSTL135 or SSTL12 Unidirectional Termination UG471_c1_49_042913 External Termination Z0 IOB IOB DIFF_SSTL18_ I II DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 DIFF_SSTL18_ I II DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 DIFF_SSTL18_ I II DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 Z0 50Ω 50Ω VTT 0 9V for DIFF_SSTL18_ I II 0 75V for D...

Page 81: ...gure 1 60 Differential SSTL18 SSTL15 SSTL135 or SSTL12 Unidirectional DCI Termination ug471_c1_50_121214 IOB DIFF_SSTL18_ I II _DCI DIFF_SSTL15_DCI DIFF_SSTL135_DCI DIFF_SSTL12_DCI DIFF_SSTL18_ I II _DCI DIFF_SSTL15_DCI DIFF_SSTL135_DCI DIFF_SSTL12_DCI DIFF_SSTL18_ I II _DCI DIFF_SSTL15_DCI DIFF_SSTL135_DCI DIFF_SSTL12_DCI RVRN 2Z0 100Ω RVRP 2Z0 100Ω DCI RVRN 2Z0 100Ω RVRP 2Z0 100Ω IOB RVRN 2Z0 10...

Page 82: ...DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 DIFF_SSTL18_II DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 DIFF_SSTL18_II DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 DIFF_SSTL18_II DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 DIFF_SSTL18_II DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 DIFF_SSTL18_II DIFF_SSTL15 _R DIFF_SSTL135 _R DIFF_SSTL12 External Termination 50Ω VTT 0 9V for DIFF_SSTL18_II 0 75V for DIFF...

Page 83: ...35 and DIFF_SSTL12 are only available for unidirectional signaling Use the T_DCI standards for bidirectional signaling of DIFF_SSTL15 DIFF_SSTL135 and DIFF_SSTL12 with DCI termination X Ref Target Figure 1 62 Figure 1 62 Differential SSTL18 Class II with DCI Bidirectional Termination Z0 IOB IOB DIFF_SSTL18_II_DCI DIFF_SSTL18_II_DCI VCCO 1 8V RVRN 2Z0 100Ω RVRP 2Z0 100Ω DCI VCCO 1 8V RVRN 2Z0 100Ω ...

Page 84: ...quires a differential amplifier input buffer and a push pull output buffer HSUL_12 and DIFF_HSUL_12 The differential DIFF_ version uses complementary single ended drivers for outputs and differential receivers for inputs X Ref Target Figure 1 63 Figure 1 63 SSTL18 SSTL15 SSTL135 or SSTL12 T_DCI Termination ug471_c1_53_021214 Z0 IOB IOB 1 0 SSTL18_II_T_DCI SSTL15_T_DCI SSTL135_T_DCI SSTL12_T_DCI SS...

Page 85: ... The differential DIFF_ versions use complementary single ended drivers for outputs and differential receivers for inputs HSUL_12 Figure 1 64 shows a sample circuit illustrating a unidirectional board topology with no termination for HSUL_12 Only HP I O banks support the DCI version Table 1 38 Available I O Bank Type HR HP N A Available X Ref Target Figure 1 64 Figure 1 64 HSUL_12 with Unidirectio...

Page 86: ...rating a board topology with no termination for differential HSUL_12 with unidirectional signalling X Ref Target Figure 1 65 Figure 1 65 HSUL_12 with Bidirectional Signalling Z0 IOB HSUL_12 ug471_c1_55_011811 Z0 IOB IOB HSUL_12_DCI HSUL_12_DCI VREF 0 60V VREF 0 60V External Termination DCI IOB HSUL_12 R0 50Ω VREF 0 60V VREF 0 60V R0 50Ω X Ref Target Figure 1 66 Figure 1 66 Differential HSUL_12 wit...

Page 87: ...a board topology with no termination for differential HSUL_12 with bidirectional signalling X Ref Target Figure 1 67 Figure 1 67 Differential HSUL_12 with Unidirectional DCI Signalling ug471_c1_57_0111811 IOB DIFF_HSUL_12_DCI DIFF_HSUL_12_DCI DCI DIFF_HSUL_12_DCI IOB Z0 Z0 R0 50Ω R0 50Ω X Ref Target Figure 1 68 Figure 1 68 Differential HSUL_12 with Bidirectional Signalling Z0 IOB IOB DIFF_HSUL_12 ...

Page 88: ...n uses complementary single ended drivers for outputs and differential receivers for inputs Summary of Memory Interface IOSTANDARDs and Attributes Supported Table 1 40 lists the available 7 series FPGA single ended HSTL SSTL HSUL and MOBILE_DDR I O standards and attributes supported Table 1 41 lists the available 7 series FPGA differential HSTL SSTL HSUL and MOBILE_DDR I O standards and attributes...

Page 89: ...HSTL_II_18 HSTL_II_18 HSTL_II_18 HSTL_II_DCI N A HSTL_II_DCI N A HSTL_II_DCI_18 N A HSTL_II_DCI_18 N A N A N A HSTL_II_T_DCI N A N A N A HSTL_II_T_DCI_18 N A SSTL12 N A SSTL12 N A SSTL12_DCI N A N A N A N A N A SSTL12_T_DCI N A N A SSTL135_R N A SSTL135_R SSTL135 SSTL135 SSTL135 SSTL135 SSTL135_DCI N A N A N A N A N A SSTL135_T_DCI N A N A SSTL15_R N A SSTL15_R SSTL15 SSTL15 SSTL15 SSTL15 SSTL15_D...

Page 90: ...FF_HSTL_II_DCI_18 N A DIFF_HSTL_II_DCI_18 N A DIFF_HSTL_II_T_DCI N A DIFF_HSTL_II_T_DCI N A DIFF_HSTL_II_T_DCI_18 N A DIFF_HSTL_II_T_DCI_18 N A DIFF_SSTL12 N A DIFF_SSTL12 N A DIFF_SSTL12_DCI N A N A N A N A N A DIFF_SSTL12_T_DCI N A N A DIFF_SSTL135_R N A DIFF_SSTL135_R DIFF_SSTL135 DIFF_SSTL135 DIFF_SSTL135 DIFF_SSTL135 DIFF_SSTL135_DCI N A N A N A N A N A DIFF_SSTL135_T_DCI N A N A DIFF_SSTL15_...

Page 91: ... LVDS_25 I O standard is only available in the HR I O banks It requires a VCCO to be powered at 2 5V for outputs and for inputs when the optional internal differential termination is implemented DIFF_TERM TRUE Transmitter Termination The 7 series FPGA LVDS transmitter does not require any external termination Table 1 44 lists the allowed attributes corresponding to the 7 series FPGA LVDS current m...

Page 92: ...nternal differential termination is not used DIFF_TERM FALSE which is the default value The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet X Ref Target Figure 1 70 Figure 1 70 LVDS or LVDS_25 Receiver Termination X Ref Target Figure 1 71 Figure 1 71 LVDS or LVDS_25 With DIFF_TERM Receiver Termi...

Page 93: ...C coupled and DC biased circuit for a differential clock input RDIFF provides the 100Ω differential receiver termination because the internal DIFF_TERM is set to FALSE To maximize the input noise margin all RBIAS resistors should be the same value essentially creating a VICM level of VCCO 2 Resistors in the 10k 100KΩ range are recommended The typical values for the AC coupling capacitors CAC are i...

Page 94: ...require a parallel termination resistor either by using a discrete resistor on the PCB or by using the 7 series FPGAs DIFF_TERM attribute to enable internal termination Mini LVDS is only available in HR I O banks and requires a VCCO voltage level of 2 5V The IOSTANDARD is called MINI_LVDS_25 Table 1 48 summarizes all the possible Mini LVDS I O standards and attributes supported Table 1 45 Availabl...

Page 95: ... a differential I O standard for transmitting high speed serial data used by the DVI and HDMI video interfaces The TMDS standard requires external 50Ω pull up resistors to 3 3V on the inputs TMDS inputs do not require differential input termination resistors TMDS is only available in HR I O banks and requires a VCCO voltage level of 3 3V The IOSTANDARD is called TMDS_33 Table 1 52 summarizes all t...

Page 96: ...urce termination is required BLVDS is only available in HR I O banks and requires a VCCO voltage level of 2 5V The IOSTANDARD is called BLVDS_25 Table 1 54 summarizes all the possible BLVDS I O standards Figure 1 73 shows the BLVDS transmitter termination Table 1 53 Available I O Bank Type HR HP Available N A Table 1 54 Allowed Attributes of the BLVDS I O Standard Attributes Primitives IBUFDS IBUF...

Page 97: ...VCCO 1 8V inputs Incompatible example HSTL_I_DCI_18 VREF 0 9V and HSTL_I_DCI VREF 0 75V inputs 3 Combining input standards and output standards Input standards and output standards with the same VCCO requirement can be combined in the same bank Compatible example LVDS_25 output and LVCMOS25 input Incompatible example LVDS_25 output output VCCO 2 5V and HSTL_I_DCI_18 input input VCCO 1 8V 4 Combini...

Page 98: ...FF_HSTL_I_DCI_18 HP 1 8 1 8 N A N A DIFF_HSTL_II Both 1 5 Any N A N A DIFF_HSTL_II_18 Both 1 8 Any N A N A DIFF_HSTL_II_DCI HP 1 5 1 5 N A N A DIFF_HSTL_II_DCI_18 HP 1 8 1 8 N A N A DIFF_HSTL_II_T_DCI HP 1 5 1 5 N A N A DIFF_HSTL_II_T_DCI_18 HP 1 8 1 8 N A N A DIFF_HSUL_12 Both 1 2 Any N A N A DIFF_HSUL_12_DCI HP 1 2 1 2 N A N A DIFF_MOBILE_DDR HR 1 8 1 8 N A N A DIFF_SSTL12 HP 1 2 Any N A N A DIF...

Page 99: ... 1 8 1 8 N A 0 9 HSTL_II_T_DCI HP 1 5 1 5 N A 0 75 HSTL_II_T_DCI_18 HP 1 8 1 8 N A 0 9 HSUL_12 Both 1 2 Any N A 0 6 HSUL_12_DCI HP 1 2 1 2 N A 0 6 LVCMOS12 Both 1 2 1 2 N A N A LVCMOS15 Both 1 5 1 5 N A N A LVCMOS18 Both 1 8 1 8 N A N A LVCMOS25 HR 2 5 2 5 N A N A LVCMOS33 HR 3 3 3 3 N A N A LVDCI_15 HP 1 5 1 5 N A N A LVDCI_18 HP 1 8 1 8 N A N A LVDCI_DV2_15 HP 1 5 1 5 N A N A LVDCI_DV2_18 HP 1 8...

Page 100: ...outputs There are some important criteria that need to be considered a The optional internal differential termination is not used DIFF_TERM FALSE which is the default value unless the VCCO voltage is at the level required for outputs b The differential signals at the input pins meet the VIN requirements in the Recommended Operating Conditions table of the specific device family data sheet c The di...

Page 101: ...HP N A SLOW FAST Yes Split Split DIFF_HSTL_II_T_DCI HP N A SLOW FAST Required None Split DIFF_HSTL_II_T_DCI_18 HP N A SLOW FAST Required None Split DIFF_HSUL_12 Both N A SLOW FAST Yes None None DIFF_HSUL_12_DCI HP N A SLOW FAST Yes Driver None DIFF_MOBILE_DDR HR N A SLOW FAST Yes None None DIFF_SSTL12 HP N A SLOW FAST Yes None None DIFF_SSTL12_DCI HP N A SLOW FAST No None Split DIFF_SSTL12_T_DCI H...

Page 102: ... HP N A SLOW FAST Yes Driver None LVCMOS12 Both HP 2 4 6 8 HR 4 8 12 SLOW FAST Yes None None LVCMOS15 Both HP 2 4 6 8 12 16 HR 4 8 12 16 SLOW FAST Yes None None LVCMOS18 Both HP 2 4 6 8 12 16 HR 4 8 12 16 24 SLOW FAST Yes None None LVCMOS25 HR 4 8 12 16 SLOW FAST Yes None None LVCMOS33 HR 4 8 12 16 SLOW FAST Yes None None LVDCI_15 HP N A N A Yes Driver None LVDCI_18 HP N A N A Yes Driver None LVDC...

Page 103: ...ne SSTL18_I_DCI HP N A SLOW FAST No None Split SSTL18_II Both N A SLOW FAST Yes None None SSTL18_II_DCI HP N A SLOW FAST Yes Split Split SSTL18_II_T_DCI HP N A SLOW FAST Required None Split TMDS_33 HR N A N A No None None Notes 1 The bidirectional buffers column describes the I O standards use of a bidirectional signal The standards labeled as required can only be used with bidirectional signals a...

Page 104: ...ket Pin Planning to Mitigate SSO Sensitivity When performing pin planning of a design it is important to choose I O pin placements that separate strong outputs and or SSOs from sensitive inputs and outputs particularly asynchronous inputs Strong outputs tend to be the class II versions of HSTL and SSTL drivers PCI variants and any LVCMOS or LVTTL with drive strengths over 8 mA Sensitive inputs and...

Page 105: ...tput 3 state control IDELAY provides users control of an adjustable fine resolution delay taps ODELAY provides users control of an adjustable fine resolution delay taps SAME_EDGE output DDR mode SAME_EDGE and SAME_EDGE_PIPELINED input DDR mode Figure 2 1 shows a I O tile for the 1 8V HP banks Figure 2 2 shows an I O tile for a 3 3V HR bank The SelectIO input output and 3 state drivers are in the i...

Page 106: ...d hold time requirement The ZHOLD delay is automatically matched to the internal clock distribution delay and when used assures that the pad to pad hold time is zero The ILOGIC block supports an optional static uncompensated zero hold ZHOLD delay line on inputs to compensate for clock insertion delay The ZHOLD feature is optimized to compensate for clock insertion delays when the clocking path is ...

Page 107: ...User Guide www xilinx com 107 UG471 v1 10 May 8 2018 ILOGIC Resources X Ref Target Figure 2 3 Figure 2 3 ILOGICE2 Block Diagram UG471_c2_01_081215 O D DDLY D CE CK CKB S R Q1 Latch FF DDR Q2 OFB TFB CE1 CLK CLKB S R Q1 Q2 Send Feedback ...

Page 108: ...R page 109 for further discussion on input DDR Level sensitive latch Asynchronous combinatorial The ILOGIC block registers have a common clock enable signal CE1 that is active High by default If left unconnected the clock enable pin for any storage element defaults to the active state X Ref Target Figure 2 4 Figure 2 4 ILOGICE3 Block Diagram UG471_c2_02_081215 O ZHOLD_DELAY D DDLY D DLYFABRIC DLVI...

Page 109: ...rview IDDR 7 series devices have dedicated registers in the ILOGIC blocks to implement input double data rate DDR registers This feature is used by instantiating the IDDR primitive All clocks feeding into the I O tile are fully multiplexed i e there is no clock sharing between ILOGIC and OLOGIC blocks The IDDR primitive supports the following modes of operation OPPOSITE_EDGE mode SAME_EDGE mode SA...

Page 110: ...o the FPGA logic on the same clock edge Unlike the SAME_EDGE mode the data pair is not separated by one clock cycle However an additional clock latency is required to remove the separated effect of the SAME_EDGE mode Figure 2 7 shows the timing diagram of the input DDR using the SAME_EDGE_PIPELINED mode The output pairs Q1 and Q2 are presented to the FPGA logic at the same time X Ref Target Figure...

Page 111: ...Q1 Q2 D0A D1A D2A D0A D2A D4A D6A D8A D10A D1A D3A D5A D7A D9A D11A D3A D4A D5A D6A D7A D8A D9A D10A D11A D12A D13A X Ref Target Figure 2 8 Figure 2 8 IDDR Primitive Block Diagram Table 2 1 IDDR Port Signals Port Name Function Description Q1 and Q2 Data outputs IDDR register outputs C Clock input port The C pin represents the clock input pin CE Clock enable port The enable pin affects the loading ...

Page 112: ...set and reset pins However only one can be used per IDDR As a result S R is described instead of separate set and reset pins Table 2 2 IDDR Attributes Attribute Name Description Possible Values DDR_CLK_EDGE Sets the IDDR mode of operation with respect to clock edge OPPOSITE_EDGE default SAME_EDGE SAME_EDGE_PIPELINED INIT_Q1 Sets the initial value for Q1 port 0 default 1 INIT_Q2 Sets the initial va...

Page 113: ... D input of the input register and is reflected on the Q1 output of the input register at time TICKQ after Clock Event 1 Clock Event 4 At time TISRCK before Clock Event 4 the S R signal configured as synchronous reset in this case becomes valid high resetting the input register and reflected at the Q1 output of the IOB at time TICKQ after Clock Event 4 ILOGIC Timing Characteristics DDR Figure 2 10...

Page 114: ...ing edge of CLK the input signal becomes valid low at the D input of both registers and is reflected on the Q2 output of input register 2 at time TICKQ after Clock Event 4 no change in this case Clock Event 9 At time TISRCK before Clock Event 9 the S R signal configured as synchronous reset in this case becomes valid high resetting Q1 at time TICKQ after Clock Event 9 and Q2 at time TICKQ after Cl...

Page 115: ... sheets for delay values It can be applied to the combinatorial input path registered input path or both It can also be accessed directly from the FPGA logic IDELAY allows incoming signals to be delayed on an individual input pin basis The tap delay resolution is contiguously calibrated by the use of an IDELAYCTRL reference clock from the range specified in the 7 series FPGA data sheets TICOCKD TI...

Page 116: ...in VAR_LOAD_PIPE mode LD Input 1 Loads the IDELAYE2 primitive to the pre programmed value in VARIABLE mode In VAR_LOAD mode it loads the value of CNTVALUEIN In VAR_LOAD_PIPE mode it loads the value currently in the pipeline register CE Input 1 Enable increment decrement function INC Input 1 Increment decrement number of tap delays CINVCTRL Input 1 Dynamically inverts the clock C polarity CNTVALUEI...

Page 117: ...fer If the ODELAYE2 primitive is used in the same I O bank as the IDELAYE2 primitive C must use the same clock net for both primitives Module Load LD When in VARIABLE mode the IDELAY load port LD loads the value set by the IDELAY_VALUE attribute The default value of the IDELAY_VALUE attribute is zero When the default value is used the LD port acts as an asynchronous reset for the ILDELAY The LD si...

Page 118: ...ments synchronously to the clock C If CE is Low the delay through IDELAY will not change regardless of the state of INC When CE goes High the increment decrement operation begins on the next positive clock edge When CE goes Low the increment decrement operation ceases on the next positive clock edge The programmable delay taps in the IDELAYE2 primitive wrap around When the last tap delay is reache...

Page 119: ...number of taps in VARIABLE mode input path When IDELAY_TYPE is set to VAR_LOAD or VAR_LOAD_PIPE mode this value is ignored and assumed to be zero HIGH_PERFORMANCE_MODE Boolean FALSE or TRUE TRUE When TRUE this attribute reduces the output jitter The difference in power consumption is quantified in the Xilinx Power Estimator tool SIGNAL_PATTERN String DATA CLOCK DATA Causes the timing analyzer to a...

Page 120: ...ABLE mode this attribute determines the initial setting of the delay line In VAR_LOAD or VAR_LOAD_PIPE mode this attribute is not used and the initial value of the delay line is therefore always zero HIGH_PERFORMANCE_MODE Attribute When TRUE this attribute reduces the output jitter This reduction in jitter results in a slight increase in power dissipation from the IDELAYE2 primitive SIGNAL_PATTERN...

Page 121: ...nd Design Guidelines for more details The control pins being used in VAR_LOAD mode are described in Table 2 7 IDELAY Timing Table 2 8 shows the IDELAY switching characteristics Table 2 6 Control Pin when IDELAY_TYPE VARIABLE C LD CE INC TAP Setting 0 x x x No Change 1 1 x x IDELAY_VALUE 1 0 0 x No Change 1 0 1 1 Current Value 1 1 0 1 0 Current Value 1 1 0 0 0 No Change Table 2 7 Control Pin when I...

Page 122: ... output changes without glitches from tap 0 to tap 1 See Stability after an Increment Decrement Operation Clock Event 3 CE and INC are no longer asserted thus completing the increment operation The output remains at tap 1 indefinitely until there is further activity on the LD CE or INC pins Figure 2 13 shows an IDELAY timing diagram in VAR_LOAD mode X Ref Target Figure 2 12 Figure 2 12 IDELAY Timi...

Page 123: ...ehended by imagining the receiver data signal passing through the IDELAY tap chain If tap 0 and tap 1 are both near the center of the receiver data eye then the data sampled at tap 0 will be no different than the data sampled at tap 1 In this case the transition from tap 0 to tap 1 causes no change to the output To ensure that this is the case the increment decrement operation of IDELAY is designe...

Page 124: ...supplied REFCLK IDELAYCTRL Primitive Figure 2 14 shows the IDELAYCTRL primitive IDELAYCTRL Ports RST Reset The reset input pin RST is an active High asynchronous reset To ensure proper IDELAY and ODELAY operation IDELAYCTRL must be reset after configuration and the REFCLK signal is stable A reset pulse width TIDELAYCTRL_RPW is required REFCLK Reference Clock The reference clock REFCLK provides a t...

Page 125: ...tics As shown in Figure 2 15 the 7 series FPGA IDELAYCTRL RST is an edge triggered signal IDELAYCTRL Locations IDELAYCTRL modules exist in every I O column in every clock region An IDELAYCTRL module calibrates all the IDELAYE2 and ODELAYE2 modules within its clock region See the 7 Series FPGA Clocking User Guide for the definition of a clock region Figure 2 16 illustrates the relative locations of...

Page 126: ...tiated They contain user instantiated elements such as an output flip flop OFD or an output DDR element ODDR after place and route OLOGIC consists of two major blocks one to configure the output data path and the other to configure the 3 state control path These two blocks have a common clock CLK but different enable signals OCE and TCE Both have asynchronous and synchronous set and reset S R sign...

Page 127: ...s automatic when using OLOGIC No manual control of the mux select is needed This control is generated from the clock There is only one clock input to the ODDR primitive Falling edge data is clocked by a locally inverted version of the input clock All clocks feeding into the I O tile are fully multiplexed i e there is no clock sharing between the ILOGIC or the OLOGIC blocks The ODDR primitive suppo...

Page 128: ...ith minimal register to register delay as opposed to using the CLB registers Figure 2 19 shows the timing diagram of the output DDR using the SAME_EDGE mode Clock Forwarding Output DDR can forward a copy of the clock to the output This is useful for propagating a clock and DDR data with identical delays and for multiple clock generation where every clock load has a unique clock driver This is acco...

Page 129: ...ODDR register output C Clock input port The CLK pin represents the clock input pin CE Clock enable port CE represents the clock enable pin When asserted Low this port disables the output clock on port Q D1 and D2 Data inputs ODDR register inputs S R 1 Set Reset Synchronous Asynchronous set reset pin Set Reset is asserted High Notes 1 The ODDR primitive contains both set and reset pins However only...

Page 130: ...nable signal becomes valid high at the OCE input of the output register enabling the output register for incoming data Table 2 12 OLOGIC Switching Characteristics Symbol Description Setup Hold TODCK TOCKD D1 D2 pins Setup Hold with respect to CLK TOOCECK TOCKOCE OCE pin Setup Hold with respect to CLK TOSRCK TOCKSR S R pin Setup Hold with respect to CLK TOTCK TOCKT T1 T2 pins Setup Hold with respec...

Page 131: ...ling edges of CLK as well as meeting the register setup time relative to both clock edges At time TODCK before Clock Event 1 rising edge of CLK the data signal D1 becomes valid high at the D1 input of ODDR register and is reflected on the OQ output at time TOCKQ after Clock Event 1 Clock Event 2 At time TODCK before Clock Event 2 falling edge of CLK the data signal D2 becomes valid high at the D2 ...

Page 132: ...t of the 3 state register enabling the 3 state register for incoming data At time TOTCK before Clock Event 1 the 3 state signal becomes valid high at the T input of the 3 state register returning the pad to high impedance at time TOCKQ after Clock Event 1 Clock Event 2 At time TOSRCK before Clock Event 2 the S R signal configured as synchronous reset in this case becomes valid high resetting the 3...

Page 133: ... T1 input of 3 state register and is reflected on the TQ output at time TOCKQ after Clock Event 1 Clock Event 2 At time TOTCK before Clock Event 2 falling edge of CLK the 3 state signal T2 becomes valid high at the T2 input of 3 state register and is reflected on the TQ output at time TOCKQ after Clock Event 2 no change at the TQ output in this case Clock Event 9 At time TOSRCK before Clock Event ...

Page 134: ...ive Figure 2 25 shows the ODELAYE2 primitive Table 2 13 lists the available ports in the ODELAYE2 primitive X Ref Target Figure 2 25 Figure 2 25 ODELAYE2 Primitive C DATAOUT INC CE CLKIN ODATAIN REGRST LD CINVCTRL CNTVALUEIN 4 0 LDPIPEEN CNTVALUEOUT 4 0 ODELAYE2 ug471_c2_23_0118 Table 2 13 ODELAYE2 Primitive Ports Port Name Direction Width Function C Input 1 Clock input used in VARIABLE VAR_LOAD o...

Page 135: ...must be connected to the same clock as used in the SelectIO logic resources For example when using the OSERDESE2 C is connected to the same clock as CLKDIV If the IDELAYE2 primitive is used in the same I O bank as the ODELAYE2 primitive C must use the same clock net for both primitives Module Load LD When in VARIABLE mode the ODELAY load port LD loads the delay primitive to a value set by the ODEL...

Page 136: ...his interface is only available when ODELAY is in VARIABLE VAR_LOAD or VAR_LOAD_PIPE mode As long as CE remains High ODELAY will increment or decrement by TIDELAYRESOLUTION every clock C cycle The state of INC determines whether ODELAY will increment or decrement INC 1 increments INC 0 decrements synchronously to the clock C If CE is Low the delay through ODELAY will not change regardless of the s...

Page 137: ...lues VARIABLE delay dynamically adjusts the delay value VAR_LOAD_PIPE is similar to VAR_LOAD mode with the ability to store the CNTVALUEIN value for future use ODELAY_VALUE Integer 0 to 31 0 Specifies the fixed number of delay taps in fixed mode or the initial starting number of taps in VARIABLE mode output path When ODELAY_TYPE is set to VAR_LOAD or VAR_LOAD_PIPE mode this value is ignored and as...

Page 138: ...ock signal is periodic in nature and does not have long sequences of consecutive ones or zeroes while data is random in nature and can have long and short sequences of ones and zeroes ODELAY Modes When used as ODELAY the data input comes from either IBUF or the FPGA logic and the output goes to ILOGICE2 ISERDESE2 or ILOGICE3 ISERDESE2 There are four modes of operation available Fixed delay mode OD...

Page 139: ...in Table 2 7 ODELAY Timing Table 2 17 shows the ODELAY switching characteristics Figure 2 26 shows an ODELAYE2 ODELAY_TYPE VARIABLE ODELAY_VALUE 0 and DELAY_SRC CLKIN ODATAIN timing diagram Table 2 16 Control Pin when ODELAY_TYPE VAR_LOAD C LD CE INC CNTVALUEIN CNTVALUEOUT TAP Setting 0 x x x x No Change No Change 1 1 x x CNTVALUEIN CNTVALUEIN CNTVALUEIN 1 0 0 x x No Change No Change 1 0 1 1 x Cur...

Page 140: ...ng and CNTVALUEOUT are at an unknown value Clock Event 1 On the rising edge of C LD is detected as High causing the output DATAOUT to be equal to the CNTINVALUE and changing the tap setting to tap 2 The CNTVALUEOUT is updated to represent the new tap value Clock Event 2 A pulse on CE and INC are captured on the rising edge of C This indicates an increment operation The output changes without glitc...

Page 141: ...nsition from tap 0 to tap 1 causes no change to the output To ensure that this is the case the increment decrement operation of ODELAY is designed to be glitchless The user can therefore dynamically adjust the ODELAY tap setting in real time while live user data is passing through the ODELAYE2 primitive The adjustments do not disrupt the live user data as long as the current delay line value is ne...

Page 142: ...142 www xilinx com 7 Series FPGAs SelectIO Resources User Guide UG471 v1 10 May 8 2018 Chapter 2 SelectIO Logic Resources Send Feedback ...

Page 143: ... to parallel converter with specific clocking and logic features designed to facilitate the implementation of high speed source synchronous applications The ISERDESE2 avoids the additional timing complexities encountered when designing deserializers in the FPGA fabric ISERDESE2 features include Dedicated deserializer serial to parallel converter The ISERDESE2 deserializer enables high speed data t...

Page 144: ... for networking interfaces Dedicated support for DDR3 interfaces Dedicated support for QDR interfaces Dedicated support for asynchronous interfaces Figure 3 1 shows the block diagram of the ISERDESE2 highlighting all the major components and features of the block including the optional inverters X Ref Target Figure 3 1 Figure 3 1 ISERDESE2 Block Diagram UG471_c3_01_080210 OFB O IOB Multiplexers DD...

Page 145: ...Y OFB Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 SHIFTOUT1 SHIFTOUT2 O ISERDESE2 Primitive Table 3 1 ISERDESE2 Port List and Definitions Port Name Type Width Description Q1 Q8 Output 1 each Registered outputs See Registered Outputs Q1 to Q8 O Output 1 Combinatorial output See Combinatorial Output O SHIFTOUT1 Output 1 Carry out for data width expansion Connect to SHIFTIN1 of slave IOB See ISERDESE2 Width Expansion SH...

Page 146: ...ect to inverted CLK unless in MEMORY_QDR mode See MEMORY_QDR Interface Type CE1 CE2 Input 1 each Clock enable inputs See Clock Enable Inputs CE1 and CE2 RST Input 1 Active High reset See Reset Input RST CLKDIV Input 1 Divided clock input Clocks delay element deserialized data Bitslip submodule and CE unit See Divided Clock Input CLKDIV CLKDIVP Input 1 Only supported via the MIG tool Sourced by PHA...

Page 147: ...DIV when asserted active High Subsequently the data seen on the Q1 to Q8 output ports will shift as in a barrel shifter operation one position every time Bitslip is invoked DDR operation is different from SDR See BITSLIP Submodule for more details Clock Enable Inputs CE1 and CE2 Each ISERDESE2 block contains an input clock enable module Figure 3 4 X Ref Target Figure 3 3 Figure 3 3 Bit Ordering on...

Page 148: ... and CE2 ports are available When NUM_CE 1 only CE1 is available and functions as a regular clock enable High Speed Clock Input CLK The high speed clock input CLK is used to clock in the input serial data stream High Speed Clock Input CLKB The high speed secondary clock input CLKB is used to clock in the input serial data stream In any mode other than MEMORY_QDR connect CLKB to an inverted version...

Page 149: ...er from CLK to OCLK is shown in the Figure 3 5 block diagram The timing of the domain transfer is set by the user by adjusting the delay of the strobe signal to the CLK input e g using IDELAY Examples of setting the timing of this domain transfer for MEMORY_DDR3 and MEMORY_QDR modes are given in the Memory Interface Generator MIG When INTERFACE_TYPE is NETWORKING this port is unused Reset Input RS...

Page 150: ... on CLKDIV pin See Dynamic Clock Inversions Boolean TRUE or FALSE FALSE DYN_CLK_INV_EN Enables DYNCLKSEL inversion when TRUE and disables HDL inversions on CLK and CLKB pins See Dynamic Clock Inversions Boolean TRUE or FALSE FALSE INTERFACE_TYPE Chooses the ISERDESE2 use model See INTERFACE_TYPE Attribute String MEMORY MEMORY_DDR3 MEMORY_QDR OVERSAMPLE or NETWORKING MEMORY NUM_CE Defines the numbe...

Page 151: ...memory mode INTERFACE_TYPE Attribute The INTERFACE_TYPE attribute determines whether the ISERDESE2 is configured in memory or networking mode The allowed values for this attribute are MEMORY MEMORY_DDR3 MEMORY_QDR OVERSAMPLE or NETWORKING The default mode is MEMORY Figure 3 5 illustrates the ISERDESE2 internal connections when in MEMORY mode SRVAL_Q2 Sets the value after reset of the second sample...

Page 152: ...is important in the serial to parallel conversion process CLK and CLKDIV are ideally phase aligned within a tolerance There are several clocking arrangements within the FPGA to help the design meet the phase relationship requirements of CLK and CLKDIV The CLK and CLKDIV inputs must be nominally phase aligned For example if CLK and CLKDIV in Figure 3 6 were inverted by the designer at the ISERDESE2...

Page 153: ...IV inputs must be nominally phase aligned No phase relationship between CLK and OCLK is expected Calibration must be performed for reliable data transfer from CLK to OCLK domain High Speed Clock for Strobe Based Memory Interfaces and Oversampling Mode OCLK gives further information about transferring data between CLK and OCLK MEMORY_QDR Interface Type The MEMORY_QDR mode has a complex clocking str...

Page 154: ... BUFGs are driven from a single MMCM In either case the effective clocking is CLK 0 OCLK 90 CLKB 180 OCLKB 270 X Ref Target Figure 3 7 Figure 3 7 Logical View of ISERDESE2 Primitive in Oversample Mode UG471_c3_07_021914 DDLY CE2 CE1 CLKDIV DYNCLKSEL DYNCLKDIVSEL SHIFTIN1 SHIFTIN2 RST D BITSLIP OFB CLK REG D Q CLKB REG D CLK CLK CLK CLK CLK CLK CLK CLK Q REG D Q OCLKB REG D Q REG D Q REG D Q REG IS...

Page 155: ...RDES slave ports Q3 Q4 are used for the last two bits of the parallel interface For a differential input the master ISERDESE2 must be on the positive _P pin side of the differential input pair When the input is not differential the input buffer associated with the slave ISERDESE2 is not available and so cascading cannot be used Guidelines for Expanding the Serial to Parallel Converter Bit Width 1 ...

Page 156: ...in conjunction with DYN_CLK_SEL_EN and DYN_CLKDIV_SEL_EN respectively can enable the user to dynamically switch the polarity of the respective clock source This operation causes the clock going into ISERDESE2 to switch asynchronously and will likely cause the ISERDESE2 to produce erroneous data until the ISERDESE2 is reset This operation can only be supported in MEMORY_QDR and MEMORY_DDR3 mode ISE...

Page 157: ...E2 timing diagram for the input data to the ISERDESE2 The timing parameter names change for different modes SDR DDR However the Table 3 4 IOBDELAY Attribute Value on the Associated IOBDELAY Block 1 IOBDELAY Value Combinatorial Output O Registered Output Q1 Q8 NONE D D IBUF DDLY D IFD D DDLY BOTH DDLY DDLY Notes 1 When both D and DDLY are connected to ISERDESE2 Table 3 5 ISERDESE2 Switching Charact...

Page 158: ... used for word alignment purposes in source synchronous networking type applications Bitslip reorders the parallel data in the ISERDESE2 block allowing every combination of a repeating serial pattern received by the deserializer to be presented to the FPGA fabric This repeating serial pattern is typically called a training pattern training patterns are supported by many networking and telecommunic...

Page 159: ... cycles Bitslip must be deasserted for at least one CLKDIV cycle between two Bitslip assertions In both SDR and DDR mode the total latency from when the ISERDESE2 captures the asserted Bitslip input to when the bit slipped ISERDESE2 outputs Q1 Q8 are sampled into the FPGA logic by CLKDIV is two CLKDIV cycles From an applications perspective a single Bitslip command must be issued for one CLKDIV cy...

Page 160: ...CDAB has been sampled into the input side registers of the ISERDESE2 The Bitslip pin is not asserted the word propagates through the ISERDESE2 without any realignment Clock Event 2 The Bitslip pin is asserted which causes the Bitslip controller to shift all bits internally by one bit to the right Bitslip is held High for one only one CLKDIV cycle Clock Event 3 Three CLKDIV cycles after asserting B...

Page 161: ... converter in one OSERDESE2 blocks receives two to eight bits of parallel data from the fabric 14 bits if using OSERDESE2 Width Expansion serializes the data and presents it to the IOB via the OQ outputs Parallel data is serialized from lowest order data input pin to highest i e data on the D1 input pin is the first bit transmitted at the OQ pins The data parallel to serial converter is available ...

Page 162: ...r for 3 state control of the IOB Unlike data conversion the 3 state converter can only serialize up to four bits of parallel 3 state signals The 3 state converter cannot be cascaded OSERDESE2 Primitive The OSERDESE2 primitive is shown in Figure 3 14 X Ref Target Figure 3 14 Figure 3 14 OSERDESE2 Primitive UG471_c3_14_041712 TCE CLK OCE TBYTEIN RST SHIFTIN1 SHIFTIN2 OQ OFB TQ TFB TBYTEOUT SHIFTOUT1...

Page 163: ...utput to IOB See 3 state Control Output TQ TFB Output 3 state control output to fabric See 3 state Control Output TFB SHIFTOUT1 Output 1 Carry output for data width expansion Connect to SHIFTIN1 of master OSERDESE2 See OSERDESE2 Width Expansion SHIFTOUT2 Output 1 Carry output for data width expansion Connect to SHIFTIN2 of master OSERDESE2 See OSERDESE2 Width Expansion CLK Input 1 High speed clock...

Page 164: ...ing a second OSERDESE2 in SLAVE mode See OSERDESE2 Width Expansion Refer to Figure 3 3 page 147 for bit ordering at the inputs and output of the OSERDESE2 along with the corresponding bit order of the ISERDESE2 Reset Input RST When asserted the reset input causes the outputs of all data flip flops in the CLK and CLKDIV domains to be driven low asynchronously When deasserted synchronously with CLKD...

Page 165: ...e signal applied to the T1 input is asynchronous to all other signals because it simply passes through the OSERDESE2 Table 3 7 OSERDESE2 Attribute Summary Attribute Description Value Default Value DATA_RATE_OQ Defines whether data OQ changes at every clock edge or every positive clock edge with respect to CLK String SDR or DDR DDR DATA_RATE_TQ Defines whether the 3 state TQ changes at every clock ...

Page 166: ...is attribute depend on the DATA_RATE_TQ attribute When DATA_RATE_TQ is set to SDR or BUF the TRISTATE_WIDTH attribute can only be set to 1 When DATA_RATE_TQ is set to DDR the possible values for the TRISTATE_WIDTH attribute are 1 and 4 TRISTATE_WIDTH cannot be set to widths larger than 4 When a DATA_WIDTH is larger than four set the TRISTATE_WIDTH to 1 Table 3 8 shows the valid setting and combina...

Page 167: ...ot available and width expansion cannot be used When using complementary single ended standards e g DIFF_HSTL and DIFF_SSTL width expansion might not be used This is because both OLOGICE2 3 blocks in an I O tile are used by the complementary single ended standards to transmit the two complementary signals leaving no OLOGICE2 3 blocks available for width expansion purposes Figure 3 15 illustrates a...

Page 168: ...ing width expansion are listed in Table 3 10 Output Feedback The OSERDESE2 pin OFB has two functions As a feedback path to the ISERDESE2 OFB pin See ISERDESE2 Feedback from OSERDESE2 As a connection to the ODELAYE2 The output of the OSERDESE2 can be routed though the OFB pin and then delayed through the ODELAYE2 OSERDESE2 Latencies DEFAULT Interface Type Latencies The input to output latencies of ...

Page 169: ..._WIDTH Latency SDR 2 1 1 CLK cycle 3 1 2 CLK cycles 4 1 3 CLK cycles 5 1 4 CLK cycles 6 1 5 CLK cycles 7 1 6 CLK cycles 8 1 7 CLK cycles DDR 4 1 2 CLK cycles 6 1 3 CLK cycles 8 1 4 CLK cycles 10 1 5 CLK cycles 14 1 5 CLK cycles Table 3 12 OSERDESE2 Switching Characteristics Symbol Description Setup Hold TOSDCK_D TOSCKD_D D input Setup Hold with respect to CLKDIV TOSDCK_T TOSCKD_T T input Setup Hol...

Page 170: ...f the OSERDESE2 after some propagation delay Clock Event 2 On the rising edge of CLKDIV the word AB is sampled into the OSERDESE2 from the D1 and D2 inputs Clock Event 3 The data bit A appears at OQ one CLK cycle after AB is sampled into the OSERDESE2 This latency is consistent with the Table 3 11 listing of a 2 1 SDR mode OSERDESE2 latency of one CLK cycle X Ref Target Figure 3 16 Figure 3 16 OSE...

Page 171: ...DESE2 Clock Event 2 On the rising edge of CLKDIV the word ABCDEFGH is sampled into the OSERDESE2 from the D1 D8 Clock Event 3 The data bit A appears at OQ four CLK cycles after ABCDEFGH is sampled into the OSERDESE2 This latency is consistent with the Table 3 11 listing of a 8 1 DDR mode OSERDESE2 latency of four CLK cycles The second word IJKLMNOP is sampled into the OSERDESE2 from the D1 D8 X Re...

Page 172: ...er Serialization The operation of a 3 state controller is illustrated in Figure 3 18 The example is a 4 1 DDR case shown in a bidirectional system where the IOB must be frequently 3 stated Clock Event 1 T1 T2 and T4 are driven Low to release the 3 state condition The serialization paths of T1 T4 and D1 D4 in the OSERDESE2 are identical including latency such that the bits EFGH are always aligned w...

Page 173: ... the input and output SERDES elements which is their most common use However regardless of their location IO_FIFOs can also interface to resources in the FPGA fabric and other I O banks see UG475 7 Series FPGAs Packaging and Pinout Specifications for byte group pin arrangements This section focuses on the use of IO_FIFOs to interface with IOI components For external data flowing into the FPGA an I...

Page 174: ...es the FIFO to have 12 4 bit wide data inputs D and 12 4 bit wide data outputs Q The D0 3 0 D9 3 0 ports map to the Q0 3 0 Q9 3 0 ports D5 7 4 and D6 7 4 are the two extra data input ports D10 3 0 and D11 3 0 and map to the Q5 7 4 and Q6 7 4 extra output ports Q10 3 0 and Q11 3 0 The other Qn 7 4 ports are not used Table 3 13 shows the 4 x 4 mode mapping in detail X Ref Target Figure 3 19 Figure 3...

Page 175: ...f the input data Table 3 14 shows the 4 x 8 mode mapping in detail Both modes support the FULL EMPTY ALMOSTFULL and ALMOSTEMPTY flags IN_FIFO Primitive The IN_FIFO primitive is shown in Figure 3 20 D5 3 0 Q5 3 0 D6 3 0 Q6 3 0 D7 3 0 Q7 3 0 Q7 7 4 D8 3 0 Q8 3 0 Q8 7 4 D9 3 0 Q9 3 0 Q9 7 4 D10 3 0 is D5 7 4 Q5 7 4 D11 3 0 is D6 7 4 Q6 7 4 Table 3 14 IN_FIFO Input to Output Data Mapping in 4 x 8 Mode...

Page 176: ...n 4 x 4 mode Connect to ILOGIC if used for external interfaces D5 7 4 D6 7 4 I Supplemental data in ports D10 and D11 Used only in 4 x 4 mode Data on the ports appears on corresponding output ports Q5 7 4 and Q6 7 4 RDEN I Read enable WREN I Write enable Q0 7 0 Q9 7 0 O Ten 8 bit data out buses in 4 x 8 mode or ten 4 bit data out buses in 4 x 4 mode Connect to fabric if used for external interface...

Page 177: ... x 8 mode is generally Q5 7 4 Q6 7 4 O Supplemental data out ports Q10 and Q11 Used only in 4x4 mode Data on these ports is sourced from corresponding input ports D5 7 4 and D6 7 4 EMPTY O Empty flag Synchronized to RDCLK FULL O Full flag Synchronized to WRCLK ALMOSTEMPTY 1 O Programmable level empty flag Synchronized to RDCLK ALMOSTFULL 1 O Programmable level full flag Synchronized to WRCLK Notes...

Page 178: ...f the width of the input data Table 3 17 shows the 8 x 4 mode mapping in detail Both modes support the FULL EMPTY ALMOSTFULL and ALMOSTEMPTY flags OUT_FIFO Primitive The OUT_FIFO primitive is shown in Figure 3 21 Table 3 17 OUT_FIFO Input to Output Data Mapping Mapping Not Used D0 7 0 Q0 3 0 D1 7 0 Q1 3 0 D2 7 0 Q2 3 0 D3 7 0 Q3 3 0 D4 7 0 Q4 3 0 D5 7 0 Q5 3 0 D6 7 0 Q6 3 0 D7 7 0 Q7 3 0 D8 7 0 Q8...

Page 179: ...a in ports in 4 x 4 mode Connect to fabric if used for external interfaces D5 7 4 D6 7 4 I Supplemental data in ports D10 and D11 Used only in 4 x 4 mode Data on the ports appears on corresponding output ports Q5 7 4 and Q6 7 4 RDEN I Read enable WREN I Write enable Q0 3 0 Q9 3 0 O Ten 4 bit data output buses Connect to OLOGIC if used for external interfaces D0 7 0 EMPTY D1 7 0 D2 7 0 D3 7 0 D4 7 ...

Page 180: ...ere is only one word remaining to read or write A value of 2 indicates that two words are remaining to read or write Due to the asynchronous nature of the IO_FIFO and internal synchronization the flags might be overly pessimistic During a read operation there might be more data stored than is indicated by an ALMOSTEMPTY flag output of 1 or 2 During a write operation there can be more space availab...

Page 181: ...nput bits and 4 or 8 output bits per port ARRAY_MODE OUT_FIFO String ARRAY_MODE_8_X_4 ARRAY_MODE_4_X_4 ARRAY_MODE_8_X_4 Defines 4 or 8 input bits and 4 output bits per port ALMOST_EMPTY_VALUE Integer 1 or 2 1 See ALMOST EMPTY and ALMOST FULL Flags page 180 ALMOST_FULL_VALUE Integer 1 or 2 1 See ALMOST EMPTY and ALMOST FULL Flags page 180 OUTPUT_DISABLE Boolean TRUE or FALSE FALSE OUT_FIFO Output d...

Page 182: ...182 www xilinx com 7 Series FPGAs SelectIO Resources User Guide UG471 v1 10 May 8 2018 Chapter 3 Advanced SelectIO Logic Resources Send Feedback ...

Page 183: ... populates with the default terminations for each I O standard if one exists Table A 1 lists all of the default terminations for each of the I O standards supported by the 7 series FPGAs when using the SSN predictor tool within the PlanAhead software For each I O pin in the design the user can specify whether to use these terminations or to have no termination Table A 1 Default Terminations for SS...

Page 184: ... Far VTT 50Ω SSTL15_T_DCI Far VTT 50Ω SSTL18_I Far VTT 50Ω SSTL18_I_DCI Far VTT 50Ω SSTL18_II Near VTT 50Ω Far VTT 50Ω SSTL18_II_DCI Far VTT 50Ω SSTL18_II_T_DCI Far VTT 50Ω BLVDS_25 Near Series 165Ω Near Differential 140Ω and Far Differential 100Ω HSLVDCI_15 None HSLVDCI_18 None LVDCI_15 None LVDCI_18 None LVDCI_DV2_15 None LVDCI_DV2_18 None LVDS Far Differential 100Ω LVDS_25 Far Differential 100Ω...

Page 185: ... these terminations TMDS_33 Far 3 3V 50Ω Notes 1 All differential versions of the HSTL SSTL HSUL and MOBILE_DDR standards e g DIFF_SSTL135 have the same termination as the single ended versions Table A 1 Default Terminations for SSN Noise Analysis by I O Standard Cont d IO Standard 1 Default Termination Send Feedback ...

Page 186: ...lel Termination to 3 3V FP_3 3_50 3 3V 50 1K Far end Parallel Termination to 3 3V FP_3 3_1000 3 3V Z 50 1K 50 Far end Parallel Termination to VTT FP_VTT_50 VTT VCCO 2 Z 50 50 50 Near end Parallel Termination to VTT 50 Far end Parallel Termination to VTT NP_VTT_50_FP_VTT_50 100 Far end Differential Termination FD_100 VTT VCCO 2 Z 50 50 100 VTT VCCO 2 50 165 Near Series 140 Near Differential 100 Far...

Page 187: ...7 Series FPGAs SelectIO Resources User Guide www xilinx com 187 UG471 v1 10 May 8 2018 Send Feedback ...

Page 188: ...188 www xilinx com 7 Series FPGAs SelectIO Resources User Guide UG471 v1 10 May 8 2018 Appendix A Termination Options for SSO Noise Analysis Send Feedback ...

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