Xantrex XTR 100-8.5, Operating Manual

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Status Byte
M370046-01 5-31
5
Standard Event Status Register (SESR)
The standard event status register sets bits for specific events during
power supply operation. All bits in the standard event status registers are
set through the error event queue. The register is defined by IEEE 488.2
register and is controlled using 488.2 common commands:
*ESE,
*ESE?
, and
*ESR?
as well as SCPI aliases for multichannel use.
Standard Event Status Enable Register
The Event Summary Enable command determines which bits in the
Standard Event Status Register are summarized in the Event Summary Bit
(ESB) of the Status Byte. This register will be cleared at power up. To
enable events, you must make the logical sum of all values for the events
that you to be reported and send this parameter in decimal format.
See Table 5-9 for values for the events to be enabled in <status-enable>
parameter.
For example, sending
*ESE 16
sets bit 4 of the Standard Event Status
Enable Register. This will cause the Event Summary bit (ESB) in the
Status Byte to be set whenever the Execution Error bit (bit 4) in the
Standard Event Status Register gets set.
Command:
*ESE <status-enable>, *ESE?
The SCPI equivalent for multichannel use:
[:]STATus[<channel(s)>]:STANdard:ENABle <status-enable>
[:]STATus[<channel(s)>]:STANdard:ENABle?
Standard Event Status Register
The Standard Event Status Register query allows you to determine the
current contents of the Standard Event Status Register. (See “Standard
Event Status Register (SESR)”. Reading this register clears it.
Command:
*ESR?
The SCPI equivalent for multichannel use:
[:]STATus[<channel(s)>]:STANdard[:EVENt]?
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