WM8581
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PP Rev 1.0 March 2006
26
For the SAIF receiver, only stereo information is processed.
Figure 18 DSP Mode A Timing Diagram - SAIF Receiver Input Data
The MSB of the left channel of the output data changes on the first falling edge of BCLK following a
low to high LRCLK transition and may be sampled on the rising edge of BCLK. The right channel data
is contiguous with the left channel data.
Figure 19 DSP Mode A Timing Diagram – PAIF/SAIF Transmitter Data
DSP MODE B
In DSP Mode B, the MSB of Channel 1 left data is sampled on the first BCLK rising edge following a
LRCLK rising edge. Channel 1 right data then follows. For the PAIF Receiver, Channels 2, 3 and 4
follow as shown in Figure 20.
Figure 20 DSP Mode B Timing Diagram – PAIF Receiver Input Data
