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WM8581

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PP Rev 1.0 March 2006

53

The recommended configuration sequences are as follows:

TO INITIALLY CONFIGURE THE SYSTEM FOR S/PDIF RECEIVER STARTUP:

1. Write appropriate calculated values (relative to oscillator frequency) to PRESCALE_A,

PRESCALE_B, PLLB_N and PLLB_K for 32/44.1/48/88.2/96kHz (modes 2/3/4) S/PDIF
receiver sample rate operation.

2.

Enable PLLA and PLLB by clearing the PLLAPD and PLLBPD bits.

3.

Enable S/PDIF receiver by clearing the SPDIFRXPD and SPDIFPD bits.

4. Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF sample

frequency and clocking mode.

5.

If indicated sample rate is 192kHz, write appropriate calculated values (relative to oscillator
frequency) to PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K (as appropriate) for
192kHz (mode 1) S/PDIF receiver sample rate operation.

TO CONFIGURE THE SYSTEM WHEN CLOCKING MODE (SAMPLE RATE) CHANGES TO OR FROM
MODE 1 (192KHZ):

Any sample rate change between clocking modes (for example, from 44.1kHz (mode 3) to 192kHz (mode 1))
will be flagged to the application processor via the INT interrupt flag. The application processor must then
read the Interrupt Status Register. If the UPD_REC_FREQ flag is set, indicating that the clocking mode has
changed, proceed as follows:

1.

Read S/PDIF Status Register REC_FREQ[1:0] bits to identify recovered S/PDIF sample rate
frequency and clocking mode.

2. Write appropriate calculated values (relative to oscillator frequency) to PRESCALE_A,

PRESCALE_B, PLLB_N and PLLB_K based on indicated recovered S/PDIF sample
frequency and clocking mode.

This procedure is only strictly necessary when switching to or from 192kHz (mode 1) because the
PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K values are the same for
32/44.1/48/88.2/96kHz (modes 2/3/4) sample rate operation. It is, however, good interrupt service
routine practice to write the appropriate PRESCALE_A, PRESCALE_B, PLLB_N and PLLB_K values
when every clocking mode change is detected.

PHASE-LOCKED LOOPS AND S/PDIF CLOCKING (HARDWARE MODE)

In hardware mode, the user has no access to the internal clocking control registers and hence a default
configuration is loaded at reset to provide maximum functionality.

The S/PDIF receiver is enabled and hence the PLLs operate in S/PDIF receiver mode and all PLL and
S/PDIF receiver control is fully automatic. All supported S/PDIF receiver sample rates can be used.

FREQMODE_x and POSTSCALE_x control is fully automatic to ensure that the MCLK output is maintained
at 256fs relative to the S/PDIF received sample rate.

In hardware mode, the OSCCLK

must

be 12MHz and hence the external crystal (or applied XIN clock) must

be 12MHz. No other OSCCLK frequencies are supported in hardware mode.

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Summary of Contents for WM8581

Page 1: ...ns S PDIF Channel Block configuration is also supported The device has two PLLs that can be configured independently to generate two system clocks for internal or external use Device control and setup is via a 2 wire or 3 wire SPI compatible serial interface The serial interface provides access to all features including channel selection volume controls mutes de emphasis S PDIF control status and ...

Page 2: ...WM8581 Product Preview w PP Rev 1 0 March 2006 2 BLOCK DIAGRAM ...

Page 3: ... DESCRIPTION 17 INTRODUCTION 17 CONTROL INTERFACE OPERATION 18 DIGITAL AUDIO INTERFACES 22 AUDIO DATA FORMATS 24 AUDIO INTERFACE CONTROL 27 DAC FEATURES 30 ADC FEATURES 37 DIGITAL ROUTING OPTIONS 38 CLOCK SELECTION 40 PHASE LOCKED LOOPS AND S PDIF CLOCKING SOFTWARE MODE 46 PHASE LOCKED LOOPS AND S PDIF CLOCKING HARDWARE MODE 53 S PDIF TRANSCEIVER 54 S PDIF TRANSMITTER 55 S PDIF RECEIVER 58 POWERDO...

Page 4: ...N CONFIGURATION ORDERING INFORMATION DEVICE TEMPERATURE RANGE PACKAGE MOISTURE SENSITIVITY LEVEL PEAK SOLDERING TEMPERATURE WM8581SEFT V 25 to 85o C 48 lead TQFP Pb free MSL1 260 C WM8581SEFT RV 25 to 85o C 48 lead TQFP Pb free tape and reel MSL1 260 C ...

Page 5: ...AIF receiver left right word clock 23 PAIFRX_BCLK Digital Input Output Primary Audio Interface PAIF receiver bit clock 24 MCLK Digital Input Output System Master clock 256 384 512 768 1024 or 1152 fs 25 DOUT Digital Output Primary Audio Interface PAIF transmitter data output 26 PAIFTX_LRCLK Digital Input Output Primary audio interface transmitter left right word clock 27 MFP1 Digital Input Output ...

Page 6: ...register SAIF_EN is set the MFPs have the function shown in column 2 Otherwise the GPOnOP registers determine the MFP function as shown in columns 3 and 4 PIN NAME HARDWARE CONTROL MODE FUNCTION 1 SECONDARY AUDIO INTERFACE FUNCTION 2 S PDIF INPUT INDEPENDENT CLOCKING 3 GENERAL PURPOSE OUTPUT FUNCTION 4 MFP1 PAIFTX_BCLK n a1 PAIFTX_BCLK2 GPO1 MFP2 ADCMCLK n a1 ADCMCLK3 GPO2 MFP3 DR1 n a1 SPDIFIN2 G...

Page 7: ...dary Audio Interface SAIF Bit Clock SAIF_LRCLK Digital Input Output Secondary Audio Interface SAIF Left Right Word Clock SPDIFIN2 3 4 Digital Input S PDIF Receiver Input GPO1 GPO7 Digital Output General Purpose Output DR1 2 3 4 Digital Input Internal Digital Routing Configuration in Hardware Mode ALLPD Digital Input Chip Powerdown in Hardware Mode C Digital Output Recovered channel bit for current...

Page 8: ...ified as MSL1 which has an unlimited floor life at 30o C 85 Relative Humidity and therefore will not be supplied in moisture barrier bags CONDITION MIN MAX Digital supply voltage 0 3V 3 63V Analogue supply voltage 0 3V 7V PLL supply voltage 0 3V 5V Voltage range digital inputs SCLK CSB SDIN only DGND 0 3V 7V Voltage range digital inputs DGND 0 3V DVDD 0 3V Voltage range analogue inputs 1 AGND 0 3V...

Page 9: ... Signal Level unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT DAC Performance Load 10kΩ 50pF 0dBFs Full scale output voltage 1 0 x VREFP 5 Vrms A weighted fs 48kHz 103 dB Unweighted fs 48kHz 100 dB A weighted fs 48kHz AVDD 3 3V 99 dB A weighted fs 96kHz 101 dB Unweighted fs 96kHz 98 dB A weighted fs 96kHz AVDD 3 3V 99 dB A weighted fs 192kHz 101 dB Unweighted fs 192kHz 98...

Page 10: ...s 96kHz 94 dB A weighted fs 96kHz AVDD 3 3V 94 dB A weighted fs 192kHz 97 dB Unweighted fs 192kHz 94 dB Signal to Noise Ratio Note 1 2 4 SNR A weighted fs 192kHz AVDD 3 3V 94 dB 1kHz 1dB Full Scale fs 48kHz 90 dB 1kHz 1dB Full Scale fs 96kHz 88 dB Total Harmonic Distortion THD 1kHz 1dB Full Scale fs 192kHz 85 dB Dynamic Range DNR 60dB FS 100 ADC Channel Separation 1kHz Input 100 dB Channel Level M...

Page 11: ...put XTI LOW level VXIL 0 557 mV Input XTI HIGH level VXIH 853 mV Input XTI capacitance CXJ 3 32 4 491 pF Input XTI leakage IXleak 28 92 38 96 mA Output XTO LOW VXOL 15pF load capacitors 86 278 mV Output XTO HIGH VXOH 15pF load capacitors 1 458 1 942 V Supply Current Analogue supply current AVDD VREFP 5V 45 mA Analogue supply current AVDD VREFP 3 3V 30 mA Digital supply current DVDD 3 3V 16 mA Powe...

Page 12: ...cy spectrum is attenuated outside audio band 5 Channel Separation dB Also known as Cross Talk This is a measure of the amount one channel is isolated from the other Normally measured by sending a full scale signal down one channel and measuring the other 6 Pass Band Ripple Any variation of the frequency response in the pass band region MASTER CLOCK TIMING ADCMCLK MCLK tMCLKL tMCLKH tMCLKY Figure 1...

Page 13: ...r Mode fs 48kHz MCLK and ADCMCLK 256fs unless otherwise stated PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information PAIFTX_LRCLK PAIFRX_LRCLK SAIF_LRCLK propagation delay from PAIFTX_BCLK PAIFRX_BCLK SAIF_BCLK falling edge tDL 0 10 ns DOUT SAIF_DOUT propagation delay from PAIFTX_BCLK SAIF_BCLK falling edge tDDA 0 10 ns DIN1 2 3 4 SAIF_DIN setup time to PAIFRX_BCLK ...

Page 14: ...LK PAIFRX_BCLK SAIF_BCLK pulse width high tBCH 20 ns PAIFTX_BCLK PAIFRX_BCLK SAIF_BCLK pulse width low tBCL 20 ns PAIFTX_LRCLK PAIFRX_LRCLK SAIF_BCLK set up time to PAIFTX_BCLK PAIFRX_BCLK SAIF_BCLK rising edge tLRSU 10 ns PAIFTX_LRCLK PAIFRX_LRCLK SAIF_LRCLK hold time from PAIFTX_BCLK PAIFRX_BCLK SAIF_BCLK rising edge tLRH 10 ns DIN1 2 3 4 SAIF_DIN set up time to PAIFRX_BCLK SAIF_BCLK rising edge...

Page 15: ...y cycle 40 60 60 40 ns SDIN to SCLK set up time tDSU 20 ns SDIN hold time from SCLK rising edge tDHO 20 ns SDO propagation delay from SCLK rising edge tDL 5 ns CSB pulse width high tCSH 20 ns CSB rising falling to SCLK rising tCSS 20 ns Pulse width of spikes that will be suppressed tps 2 8 ns Table 6 3 wire SPI Compatible Control Interface Input Timing Information CONTROL INTERFACE TIMING 2 WIRE M...

Page 16: ... Information SCLK Frequency 0 526 kHz SCLK Low Pulse Width t1 1 3 us SCLK High Pulse Width t2 600 ns Hold Time Start Condition t3 600 ns Setup Time Start Condition t4 600 ns Data Setup Time t5 100 ns SDIN SCLK Rise Time t6 300 ns SDIN SCLK Fall Time t7 300 ns Setup Time Stop Condition t8 600 ns Data Hold Time t9 900 ns Pulse width of spikes that will be suppressed tps 0 5 ns Table 7 2 Wire Control...

Page 17: ...eption of 32 bit Right Justified Operation using system clocks of 128fs 192fs 256fs 384fs 512fs 768fs or 1152fs is provided In Slave mode selection between clock rates is automatically controlled In master mode the master clock to sample rate ratio is set by register control Sample rates fs from less than 8ks s up to 192ks s are permitted providing the appropriate system clock is input The S PDIF ...

Page 18: ...ng that the control interface input signals CSB SCLK and SDIN may have an input high level of 5V while DVDD is 3V Input thresholds are determined by DVDD 3 WIRE SPI COMPATIBLE SERIAL CONTROL MODE WITH READ BACK SDIN is used to program data SCLK is used to clock in the program data and CSB is used to latch the program data SDIN is sampled on the rising edge of SCLK The 3 wire interface write protoc...

Page 19: ...ode enabled R52 READBACK 34h 4 READEN 0 Read back mode enable 0 read back mode disabled 1 read back mode enabled Table 9 Read back Control Register The 3 wire interface readback protocol is shown below Note that the SDO pin is tri state unless CSB is held low therefore CSB must be held low for the duration of the read Figure 7 3 Wire SPI Compatible Interface Continuous Readback If CONTREAD is set ...

Page 20: ...f control data B15 to B8 i e the WM8581 register address plus the first bit of register data The WM8581 then acknowledges the first data byte by pulling SDIN low for one clock pulse The controller then sends the second byte of control data B7 to B0 i e the remaining 8 bits of register data and the WM8581 acknowledges again by pulling SDIN low The transfer of data is complete when there is a low to...

Page 21: ...l register see Table 9 to set READEN and CONTREAD to 1 and to set the READMUX bits to select the register to be read back The status of this register can then be readback using the protocol shown in Figure 10 Figure 10 2 Wire Continuous Readback If CONTREAD is set to zero the user can read back directly from the register by writing to the register address to which the device will respond with data...

Page 22: ...he audio interfaces is described below MASTER AND SLAVE MODES The Audio Interfaces require both a left right clock LRCLK and a bit clock BCLK These can be supplied externally slave mode or they can be generated internally master mode When in master mode the BCLKs and LRCLKs for an interface are output on the corresponding BCLK and LRCLK pins By default all interfaces operate in slave mode but can ...

Page 23: ...z 12 288 18 432 24 576 36 864 Unavailable Unavailable Unavailable 192kHz 24 576 36 864 Unavailable Unavailable Unavailable Unavailable Unavailable Table 12 Master Mode MCLK LRCLK Frequency Selection REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 PAIF 1 09h 2 0 PAIFRX_RATE 2 0 010 R10 PAIF 2 0Ah 2 0 PAIFTX_RATE 2 0 010 R11 SAIF 1 0Bh 2 0 SAIF_RATE 2 0 010 Master Mode MCLK LRCLK Ratio 000 128fs 0...

Page 24: ...must be time multiplexed and input on the input data line on the Audio Interface For the PAIF Receiver all four left right DAC channels are multiplexed on DIN1 assuming DAC_SEL 00 LRCLK is used as a frame synchronisation signal to identify the MSB of the first word The minimum number of BCLKs per LRCLK period is eight times the selected word length Any mark to space ratio is acceptable on LRCLK pr...

Page 25: ... following an LRCLK transition and may be sampled on the next rising edge of BCLK LRCLKs are low during the left samples and high during the right samples Figure 16 I2 S Mode Timing Diagram DSP MODE A In DSP Mode A the MSB of Channel 1 left data is sampled on the second rising edge of BCLK following a LRCLK rising edge Channel 1 right data then follows For the PAIF Receiver Channels 2 3 and 4 foll...

Page 26: ...h LRCLK transition and may be sampled on the rising edge of BCLK The right channel data is contiguous with the left channel data Figure 19 DSP Mode A Timing Diagram PAIF SAIF Transmitter Data DSP MODE B In DSP Mode B the MSB of Channel 1 left data is sampled on the first BCLK rising edge following a LRCLK rising edge Channel 1 right data then follows For the PAIF Receiver Channels 2 3 and 4 follow...

Page 27: ...y changing the audio data format may cause erroneous operation and is not recommended Interface timing is such that the input data and LRCLK are sampled on the rising edge of the interface BCLK Output data changes on the falling edge of the interface BCLK By setting the appropriate bit clock polarity control register bits e g PAIFRXBCP the polarity of BCLK may be reversed allowing input data and L...

Page 28: ... not inverted 1 BCLK inverted 1 0 PAIFTXFMT 1 0 10 PAIF Transmitter Audio Data Format Select 11 DSP Format 10 I2 S Format 01 Left justified 00 Right justified 3 2 PAIFTXWL 1 0 10 PAIF Transmitter Audio Data Word Length 11 32 bits see Note 1 2 10 24 bits 01 20 bits 00 16 bits 4 PAIFTXLRP 0 In LJ RJ I2 S modes 0 LRCLK not inverted 1 LRCLK inverted In DSP Format 0 DSP Mode A 1 DSP Mode B R13 PAIF 4 0...

Page 29: ...de the word length is forced to 24 bits In all modes the data is signed 2 s complement The digital filters internal signal paths process 24 bit data If the device is programmed to receive 16 or 20 bit data the device pads the unused LSBs with zeros If the device is programmed into 32 bit mode the 8 LSBs are ignored 2 In 24 bit I2 S mode any data width of 24 bits or less is supported provided that ...

Page 30: ...om DIN1 01 DAC takes data from DIN2 10 DAC takes data from DIN3 11 DAC takes data from DIN4 Table 16 DAC Input Select Register DAC OVERSAMPLING CONTROL For sampling clock ratios of 256fs to 1152fs the DACs should be programmed to operate at 128 times oversampling rate For sampling clock ratios of 128fs and 192fs the DACs must be programmed to operate at 64 times oversampling rate The DACOSR regist...

Page 31: ... DAC CONTROL 2 10h 3 0 PL 3 0 1001 1111 L R 2 L R 2 Table 18 DAC Attenuation Register PL ZERO FLAG OUTPUT Each DAC channel has a zero detect circuit which detects when 1024 consecutive zero samples have been input Should both channels of a DAC indicate a zero detect or if either DACPD or DMUTE is set for that DAC then the Zero Flag for that DAC is asserted The DZFM register bits determine which Ze...

Page 32: ...8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 Store RDA1 in intermediate latch no change to output 1 Apply RDA1 and update attenuation on all channels 7 0 LDA2 7 0 11111111 0dB Digital Attenuation control for DAC2 Left Channel DACL2 in 0 5dB steps See Table 22 R22 DIGITAL ATTENUATION DACL 2 16h 8 UPDATE Not latched Controls simultaneous update of all Attenuation La...

Page 33: ...Apply gain and update attenuation on all channels Table 21 Digital Attenuation Registers Note The volume update circuit of the WM8581 has two sets of registers LDAx and RDAx These can be accessed individually or simultaneously by writing to MASTDA Master Digital Attenuation Writing to MASTDA will overwrite the contents of LDAx and RDAx L RDAx 7 0 ATTENUATION LEVEL 00 hex dB mute 01 hex 127 5dB FE ...

Page 34: ...will apply a soft mute to the input of all the DAC digital filters The MUTE pin can also be used to apply soft mute to the DAC selected by the DZFM register bits However if the MPDENB register bit is set the MUTE pin will activate a soft mute for all DACs REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3 0 DMUTE 3 0 0000 DAC channel soft mute enables DMUTE 0 1 enable soft mute on DAC1 DMUTE 1 1 ena...

Page 35: ...digital de emphasis filter may be applied to each DAC channel The de emphasis filter for each stereo channel is enabled under the control of DEEMP 3 0 DEEMP 0 enables the de emphasis filter for DAC 1 DEEMP 1 enables the de emphasis filter for DAC 2 DEEMP 2 enables the de emphasis filter for DAC 3 and DEEMP 3 enables the de emphasis filter for DAC 4 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 3 ...

Page 36: ... 7 0 PHASE 7 0 11111111 Controls phase of DAC outputs 0 non inverted 1 inverted PHASE 0 1 inverts phase of DAC1L output PHASE 1 1 inverts phase of DAC1R output PHASE 2 1 inverts phase of DAC2L output PHASE 3 1 inverts phase of DAC2R output PHASE 4 1 inverts phase of DAC3L output PHASE 5 1 inverts phase of DAC3R output PHASE 6 1 inverts phase of DAC4L output PHASE 7 1 inverts phase of DAC4R output ...

Page 37: ...the ADC is 64fs For ADC operation at 96kHz in 256fs or 384fs mode it is recommended that the user set the ADCOSR bit This changes the ADC signal processing oversampling rate from 128fs to 64fs Similarly for ADC operation at 192kHz in 128fs or 192fs mode it is recommended that the user set the ADCOSR bit to change the oversampling rate from 64fs to 32fs REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTIO...

Page 38: ...ers in the Primary Audio Interface Receiver allow the data received on any DIN pin to be routed to any DAC Any DIN pin routed to DAC1 can also be routed to the S PDIF transmitter and Secondary Audio Interface Transmitter DAC1 may also be used to convert received S PDIF data or data received from the Secondary Audio Interface DACs 2 4 take data only from the Primary Audio Interface The Audio Interf...

Page 39: ... 0 01 Primary Audio Interface Tx Source 00 S PDIF received data 01 ADC digital output data 10 SAIF Rx data R14 8 7 SAIFTX_SRC 1 0 00 Secondary Audio Interface Tx Source 00 S PDIF received data 01 ADC digital output data 11 PAIF Rx data 1 0 TXSRC 1 0 00 S PDIF Transmitter Data Source 00 S PDIF received data thru path 01 ADC digital output data 10 SAIF Rx data 11 PAIF Rx data R30 3 REAL_THRU 0 S PDI...

Page 40: ...ate module It calculates the rate based on the digital routing setup When sourcing from the PAIF Receiver PAIFRX_LRCLK internal or external is used in the rate calculation When sourcing from the SAIF Receiver SAIF_LRCLK internal or external is used in the rate calculation The SFRM_CLK is used in the rate calculation when the DAC1 sources from the S PDIF Receiver however this can be changed by sett...

Page 41: ...e PAIF Transmitter PAIFTX_LRCLK is used in the rate calculation If the ADC is sourced by the SAIF Transmitter and PAIF Transmitter has another source SAIF_LRCLK is used in the rate calculation If the S PDIF Transmitter only is sourcing the ADC then the rate is set by the ADC_RATE register bits Figure 26 ADC Clock Selection REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R8 3 2 ADC_CLKSEL 00 ADC clo...

Page 42: ...It calculates the rate based on the digital routing setup When sourcing from the S PDIF Receiver the SFRM_CLK is used in the rate calculation When sourcing from the PAIF Receiver PAIFRX_LRCLK is used in the rate calculation When sourcing from the SAIF Receiver SAIFRX_LRCLK is used in the rate calculation When sourcing the ADC the rate is determined by either the PAIFTX_LRCLK if the PAIF Tx also so...

Page 43: ...master mode LRCLK BCLK are created by the Master Mode Clock Gen module The control of this module is described on page 34 The clock supplied to this module is selected by the PAIFRXMS_CLKSEL register and can be MCLK PLLACLK or PLLBCLK Figure 28 PAIF Receiver Clock Selection REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R9 7 6 PAIFRXMS_ CLKSEL 00 PAIFRX Master Mode clock source 00 MCLK pin 01 PLLA...

Page 44: ...odule is described on page 34 The clock supplied to this module can be ADCMCLK PLLACLK PLLBCLK or MCLK and is selected by the internal signal paiftxms_clksel If the PAIF Transmitter is sourcing the S PDIF Receiver it is recommended that the interface operate in master mode For this path paiftxms_clksel selects PLLACLK For all other digital routing options paiftxms_clksel selects whichever clock th...

Page 45: ...d is selected using the SAIFMS_CLKSEL register If the digital routing has been configured such that the SAIF Transmitter is sourcing the S PDIF Receiver then PLLACLK is automatically selected and it is recommended that the interface operate in master mode However if the SAIF Transmitter sources something other than the S PDIF Receiver and the S PDIF Receiver is powered up the PLLACLK and PLLBCLK a...

Page 46: ...Ls or the S PDIF receiver is enabled the OSCCLK signal must be present to enable the PLLs to generate the necessary clock signals The oscillator uses a Pierce type oscillator drive circuit This circuit requires an external crystal and appropriate external loading capacitors The oscillator circuit contains a bias generator within the WM8581 and hence an external bias resistor is not required Crysta...

Page 47: ...eceiver Enabled In S PDIF receive mode PLLA is automatically controlled by the S PDIF receiver to allow the receiver to use PLLA to track and lock on to the incoming S PDIF data stream In this case CLK1 is automatically maintained at a constant frequency of 256fs relative to the sample rate of the recovered S PDIF stream PLLB must be configured to produce CLK2 a specific reference clock for the S ...

Page 48: ...PLLB_N must be set to specific values when the S PDIF receiver is used Refer to S PDIF Receive Mode Clocking section for details Table 39 User Mode PLL_K and PLL_N Multiplier Control Parameter PLL User Mode PLL S PDIF Receiver Mode PRESCALE_A Manual Write PRESCALE_B Value PRESCALE_B Manual Configure Specified PLLB Frequency PLLA_N Manual Automatically Controlled PLLA_K Manual Automatically Control...

Page 49: ..._B bits in conjunction with the POSTSCALE_A and POSTSCALE_B bits Each PLL is also equipped with a pre scale divider which offers frequency divide by one or two before the OSCCLK signal is input into the PLL Please refer to Table 41 for details REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 PLLA 4 03h 0 PRESCALE_A 0 R7 PLLB 4 07h 0 PRESCALE_B 0 PLL Pre scale Divider Select 0 Divide by 1 PLL inpu...

Page 50: ...f2 to PLLBCLK divider as 8 and hence will set the f2 frequency at 98 304MHz this value is within the 90 to 100MHz range and is hence acceptable POSTSCALE_B 0 FREQMODE_B 1 0 10b f2 98 304MHz 2 Calculate R Value Using the relationship R f2 f1 the value of R can be calculated R f2 f1 R 98 304 12 R 8 192 3 Calculate PLLB_N Value The value of PLLB_N is the integer whole number value of R ignoring all d...

Page 51: ...r Mode PLL Configuration Examples When considering settings not shown in this table the key configuration parameters which must be selected for optimum operation are 90MHz f2 100MHz 5 PLLx_N 13 OSCCLOCK 10 to 14 4MHz or 16 28 to 27MHz CLOCK OUTPUT CLKOUT AND MCLK OUTPUT MCLK The clock output CLKOUT pin can be used as a clock output This pin is intended to be used as a clock source pin for providin...

Page 52: ...Rates PLLB f2 94 3104MHz The FREQMODE_B 1 0 bits and POSTSCALE_B bit are not used in PLL S PDIF recever mode The PLL register settings are configured by default to allow 32 44 1 48 88 2 96kHz modes 2 3 4 sample rate S PDIF receiver operation using a 12MHz crystal clock The appropriate PLLB register values must be updated if Any crystal clock frequency other than 12MHz is used OR A S PDIF stream wi...

Page 53: ...as follows 1 Read S PDIF Status Register REC_FREQ 1 0 bits to identify recovered S PDIF sample rate frequency and clocking mode 2 Write appropriate calculated values relative to oscillator frequency to PRESCALE_A PRESCALE_B PLLB_N and PLLB_K based on indicated recovered S PDIF sample frequency and clocking mode This procedure is only strictly necessary when switching to or from 192kHz mode 1 becau...

Page 54: ...ted out of the WM8581 onto a pin for external use and may be used to clock the internal DAC as required The transmitter generates S PDIF frames where audio data may be sourced from the ADC S PDIF Receiver or the Digital Audio Interfaces S PDIF FORMAT S PDIF is a serial bi phase mark encoded data stream An S PDIF frame consists of two sub frames Each sub frame is made up of Preamble a synchronizati...

Page 55: ...r Control The WM8581 also transmits the preamble and VUCP bits Validity User Data Channel Status and Parity bits Validity Bit Set to 0 to indicate valid data unless TXSRC 00 S PDIF receiver where Validity is the value recovered from the S PDIF input stream by the S PDIF receiver User Data Set to 0 as User Data configuration is not supported in the WM8581 if TXSRC 00 S PDIF receiver User Data is th...

Page 56: ...Audio interface has no pre emphasis 001 Data from Audio interface has pre emphasis 010 Reserved Audio interface has pre emphasis 011 Reserved Audio interface has pre emphasis All other modes are reserved and should not be used R31 SPDTXCHAN 1 1Fh 7 6 CHSTMODE 1 0 7 6 00 00 Only valid mode for consumer applications Table 48 S PDIF Transmitter Channel Bit Control 1 REGISTER ADDRESS BIT LABEL CHANNEL...

Page 57: ...us Bits 23 20 00 0000 Do not use channel number 01 0001 Send to Left Channel 10 0010 Send to Right Channel R33 SPDTXCHAN 3 21h 7 6 CHNUM2 1 0 23 20 00 11 0000 Do not use channel number Table 50 S PDIF Transmitter Channel Bit Control 3 REGISTER ADDRESS BIT LABEL CHANNEL STATUS BIT DEFAULT DESCRIPTION 3 0 FREQ 3 0 27 24 0001 Sampling Frequency See S PDIF specification IEC60958 3 for details 0001 Sam...

Page 58: ...utputs GPOs The four S PDIF inputs are multiplexed to allow one input to go to the S PDIF receiver for decoding The S PDIF receiver can be powered down using the SPDIFRXD register bit REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 SPDIFIN1MODE 1 Selects the input circuit type for the SPDIFIN1 input 0 CMOS compatible input 1 Comparator input Compatible with 500mVpp AC coupled consumer S PDIF inpu...

Page 59: ...d DEEMPH channel status be set and the S PDIF receiver is routed to DAC1 the de emphasis filter is activated for DAC1 The S PDIF receiver reads channel status data from channel 1 only The channel status data is stored in five read only registers which can be read via the serial interface see Serial Interface Readback When new channel status data has been recovered and stored in registers the Chann...

Page 60: ...R46 SPDRXCHAN 3 2Eh read only 7 4 CHNUM1 3 0 23 20 Channel number for channel 1 0000 Take no account of channel number channel 1 defaults to left DAC 0001 channel 1 to left channel 0010 channel 1 to right channel Table 56 S PDIF Receiver Channel Status Register 3 REGISTER ADDRESS BIT LABEL CHANNEL STATUS BIT DEFAULT DESCRIPTION 3 0 FREQ 3 0 27 24 Sampling Frequency Refer to S PDIF specification IE...

Page 61: ...bits 16 bits 010 22 bits 18 bits 100 23 bits 19 bits 101 24 bits 20 bits 110 21 bits 17 bits 3 1 RXWL 2 0 35 33 All other combinations are reserved and may give erroneous operation Data will be truncated internally when these bits are set R48 SPDRXCHAN 5 30h read only 7 4 ORGSAMP 3 0 39 36 Original Sampling Frequency Refer to S PDIF specification IEC60958 3 for details 0000 original sampling frequ...

Page 62: ...detected 0 Sync code not detected 1 Sync code detected received data is not audio PCM S PDIF Status Register CPY_N Recovered Channel Status bit 2 active low 0 Copyright is asserted for this data 1 Copyright is not asserted for this data Channel Status Register S PDIF Status Register GPO pins DEEMPH Recovered Channel Status bit 3 0 Recovered S PDIF data has no pre emphasis 1 Recovered S PDIF data h...

Page 63: ...the S PDIF Status Register can be read to reveal the status of the flag See Table 61 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION 0 UPD_UNLOCK UNLOCK flag update signal 0 INTB not caused by update to UNLOCK flag 1 INTB caused by update to UNLOCK flag 1 INT_INVALID INVALID flag interrupt signal 0 INTB not caused by INVALID flag 1 INTB caused by INVALID flag 2 INT_CSUD CSUD flag interrupt signal 0...

Page 64: ...us Register The interrupt and update signals used to generate INTB can be masked as necessary The MASK register bit prevents flags from asserting INTB and from updating the Interrupt Status Register R43 Masked flags update the S PDIF Status Register R49 REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R37 INTMASK 25h 8 0 MASK 8 0 000000000 When a flag is masked it does not update the Interrupt Statu...

Page 65: ...hannel Status block PCM_N is set on detection of the 96 bit IEC 61937 non audio data sync code embedded in the data section of the S PDIF frame If DAC1 is sourcing the S PDIF Receiver and either the AUDIO_N or PCM_N flags are asserted DAC1 is automatically muted using the softmute feature As described above any change of AUDIO_N or PCM_N status will cause an INTB interrupt UPD_NON_AUDIO to be gene...

Page 66: ...its are powered down by setting PLLPD OSCPD and SPDIFPD respectively Setting all of ADCPD DACPD 2 0 SPDIFTXD SPDIFRXD and OUTPD 3 0 will powerdown everything except the references VMIDADC ADCREF and VMIDDAC These may be powered down by setting PWDN Setting PWDN will override all other powerdown control bits It is recommended that the ADC and DAC are powered down before setting PWDN The default is ...

Page 67: ...rcuit The POR circuit is powered from AVDD The circuit monitors DVDD and VMID and asserts PORB low if DVDD or VMID are below the minimum threshold Vpor_off On power up the POR circuit requires AVDD to be present to operate PORB is asserted low until AVDD DVDD and VMID voltages have risen above their reset thresholds When these three conditions have been met PORB is released high When PORB is relea...

Page 68: ...re DVDD SYMBOL MIN TYP MAX UNIT Vpora 0 5 0 7 1 0 V Vporr 0 5 0 7 1 1 V Vpora_off 1 0 1 4 2 0 V Vpord_off 0 6 0 8 1 0 V Table 67 Typical POR Operation In a real application the designer is unlikely to have control of the relative power up sequence of AVDD and DVDD Using the POR circuit to monitor VMID ensures a reasonable delay between applying power to the device and Device Ready ...

Page 69: ...r string and the decoupling capacitor To reduce transient audio effects during power on the stereo DACs on the WM8581 have their outputs clamped to VMID at power on This increases the capacitive loading of the VMID resistor string as the DAC output AC coupling capacitors must be charged to VMID and hence the required charge time To ensure minimum device startup time the VMIDSEL bit is set by defau...

Page 70: ...l 3 wire control Table 68 Hardware Software Mode Setup DIGITAL ROUTING CONTROL See page 22 for a more detailed explanation of the Digital Routing Options within the WM8581 In Software Control Mode the values of register bits DAC_SRC PAIFTX_SRC and TXSRC configure the signal path routing between interfaces In hardware mode similar control can be achieved via pins DR1 DR2 DR3 and DR4 as detailed in ...

Page 71: ...L AUDIO INTERFACE CONTROL In Hardware Control Mode CSB and SCLK become controls to configure the Primary Audio Interface data format and word length The configuration applies to both transmit and receive sides of the interface Table 72 below shows the options available CSB SCLK FORMAT WORD LENGTH 0 0 24 bit right justified 0 1 20 bit right justified 1 0 24 bit left justified 1 1 24 bit I2 S Table ...

Page 72: ...in a parity error or a bi phase encoding error it is assumed the sub frame has become corrupted Similarly if VALIDITY is detected as 1 it is assumed the data within the S PDIF frame is invalid Under these conditions the S PDIF Receiver repeats the last valid sample in place of the corrupted invalid samples Note For the S PDIF receiver to S PDIF transmitter path only VALIDITY errors will cause data...

Page 73: ...L 1 0 PAIFTXFMT 1 0 010001010 R14 SAIF 2 0E SAIFTX_SRC 1 0 SAIF_EN SAIFBCP SAIFLRP SAIFWL 1 0 SAIFFMT 1 0 000001010 R15 DAC CONTROL 1 0F RX2 DAC_M ODE DAC4SEL 1 0 DAC3SEL 1 0 DAC2SEL 1 0 DAC1SEL 1 0 011100100 R16 DAC CONTROL 2 10 0 IZD DZFM 2 0 PL 3 0 000001001 R17 DAC CONTROL 3 11 0 0 0 0 DEEMPALL DEEMP 3 0 000000000 R18 DAC CONTROL 4 12 0 PHASE 7 0 011111111 R19 DAC CONTROL 5 13 0 MPDENB DACATC ...

Page 74: ...EGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R0 PLLA 1 DEVID1 00h 8 0 PLLA_K 8 0 100100001 R1 PLLA 2 DEVID2 01h 8 0 PLLA_K 17 9 101111110 3 0 PLLA_K 21 18 1101 Fractional K part of PLLA input output frequency ratio treat as one 22 digit binary number Reading from these registers will return the device ID R0 returns 10000101 81h R1 returns 10000000 85h Device ID readback is not possible in continu...

Page 75: ...Hz 10 44 1KHz to 48KHz 11 32KHz 6 5 MCLKOUTSRC 00 MCLK pin output source 00 MCLK pin configured as an input The system should be powered down before changing from this register setting 01 PLLACLK 10 PLLBCLK 11 OSCCLK R7 PLLB 4 07h 8 7 CLKOUTSRC 11 CLKOUT pin source 00 no output tristate 01 PLLACLK 10 PLLBCLK 11 OSCCLK 1 0 DAC_CLKSEL 00 DAC clock source 00 MCLK pin 01 PLLACLK 10 PLLBCLK 11 MCLK pin...

Page 76: ... 011 384fs 100 512fs 101 768fs 110 1152fs 4 3 PAIFTX_BCLKSEL 1 0 00 Master Mode BCLKRate 00 64 BCLKs LRCLK 01 128 BCLKs LRCLK 10 256 BCLKs LRCLK 11 BCLK System Clock R10 PAIF 2 0Ah 5 PAIFTXMS 0 PAIF Transmitter Master Slave Mode Select 0 Slave Mode 1 Master Mode 2 0 SAIF_RATE 2 0 010 Master Mode LRCLK Rate 000 128fs 001 192fs 010 256fs 011 384fs 100 512fs 101 768fs 110 1152fs 4 3 SAIF_BCLKSEL 1 0 ...

Page 77: ...64x oversampling R12 PAIF 3 0Ch 8 7 DAC_SRC 1 0 11 DAC1 Source 00 S PDIF received data 10 SAIF Receiver data 11 PAIF Receiver data Note When DAC_SRC 00 DAC2 3 4 may be turned off depending on RX2DAC_MODE 1 0 PAIFTXFMT 1 0 10 PAIF Transmitter Audio Data Format Select 11 DSP Format 10 I2 S Format 01 Left justified 00 Right justified 3 2 PAIFTXWL 1 0 10 PAIF Transmitter Audio Data Word Length 11 32 b...

Page 78: ...ed 6 SAIF_EN 0 SAIF Enable 0 SAIF disabled 1 SAIF enabled R14 SAIF 2 0Eh 8 7 SAIFTX_SRC 1 0 00 Secondary Audio Interface Transmitter Source 00 S PDIF received data 01 ADC digital output data 11 PAIF Receiver data 1 0 DAC1SEL 1 0 00 3 2 DAC2SEL 1 0 01 5 4 DAC3SEL 1 0 10 7 6 DAC4SEL 1 0 11 DAC digital input select 00 DAC takes data from DIN1 01 DAC takes data from DIN2 10 DAC takes data from DIN3 11...

Page 79: ...etect automute enabled 3 0 DEEMP 3 0 0000 De emphasis mode select DEEMP 0 1 enable De emphasis on DAC1 DEEMP 1 1 enable De emphasis on DAC2 DEEMP 2 1 enable De emphasis on DAC3 DEEMP 3 1 enable De emphasis on DAC 4 R17 DAC CONTROL 3 11h 4 DEEMPALL 0 0 De emphasis controlled by DEEMP 3 0 1 De emphasis enabled on all DACs R18 DAC CONTROL 4 12h 5 0 PHASE 7 0 11111111 Controls phase of DAC outputs PHA...

Page 80: ... to output 1 Apply LDA2 and update attenuation on all channels 7 0 RDA2 7 0 11111111 0dB Digital Attenuation control for DAC2 Right Channel DACR2 in 0 5dB steps See Table 22 R23 DIGITAL ATTENUATION DACR 2 17h 8 UPDATE Not latched Controls simultaneous update of all Attenuation Latches 0 Store RDA2 in intermediate latch no change to output 1 Apply RDA2 and update attenuation on all channels 7 0 LDA...

Page 81: ...e only interface sourcing the ADC 000 128fs 001 192fs 010 256fs 011 384fs 100 512fs 101 768fs 110 1152fs R29 ADC CONTROL 1 1Dh 8 VMIDSEL 1 VMID Impedance Selection 0 High impedance power saving 1 Low impedance fast power on 1 0 TXSRC 1 0 10 S PDIF Transmitter Data Source 00 S PDIF received data see REAL_THROUGH 01 ADC digital output data 10 Secondary Audio Interface 11 Audio Interface received dat...

Page 82: ...Do not use channel number 01 0001 Send to Left Channel 10 0010 Send to Right Channel R33 SPDTXCHAN 3 21h 7 6 CHNUM2 1 0 00 11 0000 Do not use channel number 3 0 FREQ 3 0 0001 Sampling Frequency See S PDIF specification for details 0001 Sampling Frequency not indicated R34 SPDTXCHAN 4 22h 5 4 CLKACU 1 0 11 Clock Accuracy of Generated clock 00 Level II 01 Level I 10 Level III 11 Interface frame rate...

Page 83: ...ask control for INT_TRANS_ERR MASK 4 mask control for UPD_AUDIO_N MASK 5 mask control for UPD_PCM_N MASK 6 mask control for UPD_CPY_N MASK 7 mask control for UPD_DEEMPH MASK 8 mask control for UPD_REC_FREQ 3 0 GPO1OP 3 0 0000 7 4 GPO2OP 3 0 0001 0000 INTB 0001 V 0010 U 0011 C 0100 P 0101 SFRM_CLK 0110 192BLK 0111 UNLOCK 1000 CSUD 1001 REC_FREQ192 1010 ZFLAG 1011 NON_AUDIO 1100 CPY_N 1101 DEEMP 111...

Page 84: ...1 R41 GPO4 29h 3 0 GPO7OP 3 0 0110 0000 INTB 0001 V 0010 U 0011 C 0100 P 0101 SFRM_CLK 0110 192BLK 0111 UNLOCK 1000 CSUD 1001 REC_FREQ192 1010 ZFLAG 1011 NON_AUDIO 1100 CPY_N 1101 DEEMP 1110 Set GPO as S PDIF input standard CMOS input buffer Only applicable for GPO3 4 5 1111 Set GPO as S PDIF input comparator input for AC coupled consumer S PDIF signals Only applicable for GPO3 4 5 0 UPD_UNLOCK UN...

Page 85: ...t asserted for this data 3 DEEMPH 0 Recovered S PDIF data has no pre emphasis 1 Recovered S PDIF data has pre emphasis 5 4 Reserved Reserved for additional de emphasis modes R44 SPDRXCHAN 1 2C 7 6 CHSTMODE 1 0 00 Only valid mode for consumer applications R45 SPDRXCHAN 2 2Dh 7 0 CATCODE 7 0 Category Code Refer to S PDIF specification for details 00h indicates general mode 3 0 SRCNUM 3 0 Indicates n...

Page 86: ...nel Status bit 3 0 Recovered S PDIF data has no pre emphasis 1 Recovered S PDIF data has pre emphasis 5 4 REC_FREQ 1 0 Indicates recovered S PDIF clock frequency 00 192kHz 01 96kHz 88 2kHz 10 48kHz 44 1kHz 11 32kHz R49 SPDSTAT 31h 6 UNLOCK Indicates that the S PDIF Clock Recovery circuit is unlocked or that the input S PDIF signal is not present 0 Locked onto incoming S PDIF stream 1 Not locked to...

Page 87: ... 0 READMUX 2 0 000 Determines which status register is to be read back 000 Error Register 001 Channel Status Register 1 010 Channel Status Register 2 011 Channel Status Register 3 100 Channel Status Register 4 101 Channel Status Register 5 110 S PDIF Status Register 3 CONTREAD 0 Continuous Read Enable 0 Continuous read back mode disabled 1 Continuous read back mode enabled R52 READBACK 34h 4 READE...

Page 88: ...l Filter Characteristics DAC FILTER RESPONSES 120 100 80 60 40 20 0 0 0 5 1 1 5 2 2 5 3 Response dB Frequency Fs 0 2 0 15 0 1 0 05 0 0 05 0 1 0 15 0 2 0 0 05 0 1 0 15 0 2 0 25 0 3 0 35 0 4 0 45 0 5 Response dB Frequency Fs Figure 36 DAC Digital Filter Frequency Response 44 1 48 and 96KHz Figure 37 DAC Digital Filter Ripple 44 1 48 and 96kHz 80 60 40 20 0 0 0 2 0 4 0 6 0 8 1 Response dB Frequency F...

Page 89: ...e 32kHz Figure 41 De Emphasis Error 32KHz 10 8 6 4 2 0 0 5 10 15 20 Response dB Frequency kHz 0 4 0 3 0 2 0 1 0 0 1 0 2 0 3 0 4 0 5 10 15 20 Response dB Frequency kHz Figure 42 De Emphasis Frequency Response 44 1KHz Figure 43 De Emphasis Error 44 1KHz 10 8 6 4 2 0 0 5 10 15 20 Response dB Frequency kHz 1 0 8 0 6 0 4 0 2 0 0 2 0 4 0 6 0 8 1 0 5 10 15 20 Response dB Frequency kHz Figure 44 De Emphas...

Page 90: ...35 0 4 0 45 0 5 Response dB Frequency Fs Figure 46 ADC Digital Filter Frequency Response Figure 47 ADC Digital Filter Ripple ADC HIGH PASS FILTER The WM8581 has a selectable digital high pass filter to remove DC offsets The filter response is characterised by the following polynomial Figure 48 ADC Highpass Filter Response 1 z 1 1 0 9995z 1 H z 15 10 5 0 0 0 0005 0 001 0 0015 0 002 Response dB Freq...

Page 91: ...Product Preview WM8581 w PP Rev 1 0 March 2006 91 RECOMMENDED EXTERNAL COMPONENTS Figure 49 Recommended External Components Hardware ...

Page 92: ...WM8581 Product Preview w PP Rev 1 0 March 2006 92 Figure 50 Recommended External Components Software ...

Page 93: ...TS JEDEC 95 MS 026 VARIATION ABC REFER TO THIS SPECIFICATION FOR FURTHER DETAILS DM004 C FT 48 PIN TQFP 7 x 7 x 1 0 mm Symbols Dimensions mm MIN NOM MAX A 1 20 A1 0 05 0 15 A2 0 95 1 00 1 05 b 0 17 0 22 0 27 c 0 09 0 20 D 9 00 BSC D1 7 00 BSC E 9 00 BSC E1 7 00 BSC e 0 50 BSC L 0 45 0 60 0 75 Θ Θ Θ Θ 0 o 3 5 o 7 o Tolerances of Form and Position ccc 0 08 REF JEDEC 95 MS 026 25 36 e b 12 1 D1 D E1 ...

Page 94: ...esign WM does not warrant or represent that any license either express or implied is granted under any patent right copyright mask work right or other intellectual property right of WM covering or relating to any combination machine or process in which such products or services might be or are used WM s publication of information regarding any third party s products or services does not constitute...

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