cyber
®
reaction wheel 2
Project planning guide
Revision: 02
Doc. no.: 5022-D060586
en-33
3.4.3.1 I2C interface
The I2C bus is a master/slave bus system. The controlling microcontroller acts as the master, the
different cyber
®
reaction wheels 2 as slaves.
The I2C interface is based on two lines. The clock line (SCL) and the data line (SDA) of the
master are connected with all cyber
®
reaction wheel 2 to I2C_SCL or I2C_SDA of customer
interface B (see table 11) of the starter kit or the interface for reaction wheel D, see table 13.
I2C clock frequency:
The I2C master can be used in standard mode (= 100 kHz) and in fast mode (= 400 kHz).
I2C addressing:
The cyber
®
reaction wheel 2 uses 7 bits for addressing. The default address is 0x77 (119 dec).
This must be changed by the user during startup with the help of the cyber
®
reaction wheel
assistant as described in section 2.3.4.1 so that, for example, after a firmware update
(see section 3.6), no address is used twice in the network. The address can also be changed with
the Wittenstein software stack with ADCS without any problems. For synchronous setpoint
transmission, please observe the information in the introduction of this chapter.
3.4.3.2 SPI interface
The SPI bus is a master/slave bus system. The controlling microcontroller acts as the master, the
different cyber
®
reaction wheels 2 as slaves.
The SPI interface is based on four lines. The two data lines (MOSI, MISO) and the clock line
(SCK) are star-wired to the various reaction wheels 2 to SPI_MOSI, SPI_MISO and SPI_SCK at
customer interface B, table 11, of the starter kit or the interface to reaction wheel D, table 13.
The chip select line (nCS) is used for data transmission by the microcontroller of the selected
cyber
®
reaction wheel 2. This is why each cyber
®
reaction wheel 2 has its own chip select line.
This line is connected to SPI_nCS of the customer interface B, table 11, the starter kit or the
interface to reaction wheel D, table 13.
SPI clock frequency:
The SPI should use a clock frequency of at least 1 MHz. The maximum permitted clock frequency
is 10 MHz.
SPI settings, see figure 1.22:
Mode:
Full-Duplex Master
Frame format:
Motorola
Data size:
8 bits
First bit:
MSB (=highest bit) first
Clock Polarity (CPOL):
0
Clock Phase (CPHA):
0
