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TSW200E1
R S23 2 Interfa c e
V.35 /V.11 Interfa ce
V.3 6 /V.11 e X.2 1
Inte rfac e
DTX
DRX
DTXA
DRXA
DTXA
DRXA
DRX
DTX
DRXA
DTXA
DRXA
DTXA
RTS
CTS
DCD
DTXB
DRXB
DTXB
DRXB
DCD
RTS
CTS
DRXB
DTXB
DRXB
DTXB
DSR
DTR
RTS
CTS (A)
DCD(A)
RTSA
DCD(A)
CTS(A)
DTR
DSR
CTS (A)
DCD(A)
RTS
DCD(A)
CTS(A)
RTSA
RCK
TCKE
DSR(A)
DTR
RTSB
CTSB
DCDB
RCK
TCKE
DTR
DSR(A)
CTSB
DCDB
RTSB
RCKA
TCKEA
DSR(A)
DTRA
TCKEA
RCKA
DTRA
DSR(A)
RCKB
TCKEB
DSRB
DTRB
TCKEB
RCKB
DTRB
DSRB
TCKEA
RCKA
RCKB
TCKEB
TCKEB
RCKB
3.4 - Hierarchy of Errors and Alarms
Among the TSW200E1 test results, there are errors and alarms counters. To master the
equipment operation and to know what each counter really means, it is necessary to understand each
counter function and its hierarchy.
When there are higher priority alarms, the lower priority alarms are not displayed. This is
done to avoid counting the lower priority alarms that are caused by higher priority alarms. The
alarms are counted once each second whenever they are active, even if they do not happen for the
entire second. The errors are counted in absolute values of occurrence: each error is counted. The
exception is when a higher priority alarm becomes active, inhibiting the lower priority errors. For
example, the occurrence of FAS Error is inhibited by FAS Loss, AIS or No Signal, etc. The highest
priority alarm is the No Signal alarm.
The definition for each counter follows:
•
BIT ERROR: The counter is incremented whenever a bit error is detected on the
received pattern.
•
FAS ERROR:
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Summary of Contents for TSW200E1
Page 1: ...Operation Manual TSW200E1 Version 1 Revision 7 November 2010 ...
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