Wise TSW200E1, Manual, Page: 11 / 100

TSW200E1
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Electrical specifications:
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DC supply using NiMH rechargeable battery with 6 hours average operation and 5
and a half hours complete recharge with external AC adaptor and charger
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AC adaptor and charger - Input: 90Vac to 290Vac, 50Hz to 60Hz  5% with
automatic selection. Output: 10Vdc/1A
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Operating Temperature: 0 to 45 degrees Celsius (32 to 113 degrees Fahrenheit)
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Storage Temperature: -20 to +70 degrees Celsius (- 4 to + 158 degrees Fahrenheit)
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Relative Humidity: 95% MAX (not condensed)
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Mechanical dimensions: 24,09 x 12,59 x 5,64 cm (9,4842 x 4,9566 x 2,2204 inches)
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Weight: 1.1kg (2.4lb)
Here the general characteristics and the technical specifications of each module are
presented. Each one will be extensively covered on later sections or on other operating manuals
separately provided.
1.3.1 - BERT/BLERT Module
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S
YNCHRONOUS
M
ODE
: allows analysis of bit and block error counting, bit and block rate
errors, degraded minutes, severely errored seconds, errored seconds, error-free seconds,
available and unavailable seconds. Follows ITU-T Recommendation G.821, with speeds
from 8 Kbps up to 2048 Kbps. Allows real-time clock slips counting, following ITU-T
Recommendation G.822. If the interface is G.703-2M, the available speed is 2048 Kbps.
The bit and block errors, sync loss (PAT LOSS) and SLIP are displayed by histograms.
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Available interfaces: V.24/RS232, V.35/V.11, V.36/V.11, X.21/V.11, RS530, Co-
directional G.703 (64 kbps) and G.703 2 Mbps.
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Generated test patterns: 7 (2E3-1), 15 (2E4-1), 31 (2E5-1), 63 (2E6-1), 127(2E7-1),
127 LA, 127 LD, 511 (2E9-1), 1023 (2E10-1), 2047 (2E11-1), 2E15-1, 2E17-1,
2E18-1, 2E20-1 O153, 2E20-1 O151, QRSS, 2E21-1, 2E22-1, 2E23-1, 2E25-1,
2E28-1, 2E29-1, 2E31-1, 2E32-1, all marks (‘1111’), all spaces (‘0000’), ALT M/S
(alternating ‘1s’ and ‘0s’), Double Alt (‘1100’), 3 in 24, 1 in 16, 1 in 8, 1 in 4, D4
LA, D4 LD, USER and 7:1, in the NORMAL and INVERTED modes;
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Generated patterns for co-directional G.703 interface: 63, 511, 2047, 4095, 2E15-1,
2E20-1, 2E23-1, all marks (‘1111’), all spaces (‘0000’), ALT M/S (alternating ‘1s’
and ‘0s’) and USER, in the NORMAL and INVERTED modes;
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Internal, external and recovered reception clock to G.703-2M interface;
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Internal clock and recovered clock to co-directional G.703 interface;
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G.703-2M interface impedance: 75 unbalanced, 120  balanced or high impedance
(balanced and unbalanced);
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Test duration: continuous or timer-controlled.
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A
SYNCHRONOUS
M
ODE
: allows test execution for bit error counting ( Bit Error Rate Test ) and
for block error counting ( Block Error Rate Test ) in asynchronous communications. The rates
of bit and block errors are also displayed. Keys on the operating panel allow error insertion
and test aborting. It is also possible to obtain a distribution of errors as a function of time
using the following measurements: DEGRADED MIN (Degraded Minutes), SEV. ERR.
SEC (Severely errored seconds), ERRORED SEC (Errored seconds), ERR. FREE SEC
(error-free seconds), AVAILAB.TIME (available time) and UNAVAIL.TIME (unavailable
time) following Rec. G.821. Real-time clock SLIPS counting is done according to ITU-T
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