7
®
ADS7807
output valid data from the previous conversion on SDATA
(pin 19) synchronized to 16 clock pulses output on
DATACLK (pin 18). BUSY (pin 24) will go LOW and stay
LOW until the conversion is completed and the serial data
has been transmitted. Data will be output in Binary Two’s
Complement format, MSB first, and will be valid on both the
rising and falling edges of the data clock. BUSY going
HIGH can be used to latch the data. All convert commands
will be ignored while BUSY is LOW.
The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25
µ
s between convert com-
mands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).
STARTING A CONVERSION
The combination of CS (pin 23) and R/C (pin 22) LOW for
a minimum of 40ns puts the sample/hold of the ADS7807 in
the hold state and starts conversion ‘n’. BUSY (pin 24) will
go LOW and stay LOW until conversion ‘n’ is completed
and the internal output register has been updated. All new
convert commands during BUSY LOW will be ignored. CS
and/or R/C must go HIGH before BUSY goes HIGH or a
new conversion will be initiated without sufficient time to
acquire a new signal.
BASIC OPERATION
PARALLEL OUTPUT
Figure 1a) shows a basic circuit to operate the ADS7807
with a
±
10V input range and parallel output. Taking R/C
(pin 22) LOW for a minimum of 40ns (12
µ
s max) will
initiate a conversion. BUSY (pin 24) will go LOW and stay
LOW until the conversion is completed and the output
register is updated. If BYTE (pin 21) is LOW, the 8 most
significant bits will be valid when BUSY rises; if BYTE is
HIGH, the 8 least significant bits will be valid when BUSY
rises. Data will be output in Binary Two’s Complement
format. BUSY going HIGH can be used to latch the data.
After the first byte has been read, BYTE can be toggled
allowing the remaining byte to be read. All convert com-
mands will be ignored while BUSY is LOW.
The ADS7807 will begin tracking the input signal at the end
of the conversion. Allowing 25
µ
s between convert com-
mands assures accurate acquisition of a new signal.
The offset and gain are adjusted internally to allow external
trimming with a single supply. The external resistors com-
pensate for this adjustment and can be left out if the offset
and gain will be corrected in software (refer to the Calibra-
tion section).
SERIAL OUTPUT
Figure 1b) shows a basic circuit to operate the ADS7807
with a
±
10V input range and serial output. Taking R/C (pin
22) LOW for 40ns (12
µ
s max) will initiate a conversion and
FIGURE 1a. Basic
±
10V Operation, both Parallel and Serial
Output.
FIGURE 1b. Basic
±
10V Operation with Serial Output.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7807
Parallel Output
200
Ω
66.5k
Ω
±10V
+5V
0.1µF
NC
(1)
10µF
+
+5V
+
100
Ω
B10
B9
B8
B2
B1
B0
(LSB)
B13 B12
B15
(MSB)
Pin 21
LOW
B14
B11
B5
B4
B7
Pin 21
HIGH
NOTE: (1) SDATA (pin 19) is always active.
B6
B3
2.2µF
+
+
2.2µF
Convert Pulse
BUSY
R/C
BYTE
40ns min
1
2
3
4
5
6
7
8
9
10
11
12
13
14
NC
(1)
NC
(1)
NC
(1)
NC
(1)
NC
(1)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ADS7807
Serial Output
200
Ω
66.5k
Ω
±10V
+5V
0.1µF
NC
(1)
NC
(1)
NC
(1)
10µF
+
+5V
+
100
Ω
+
+
2.2µF
2.2µF
Convert Pulse
BUSY
40ns min
NOTE: (1) These pins should be left
unconnected.They will be active when
R/C is HIGH.
R/C
SDATA
DATACLK
