VXI Technology VM1548C, User Manual

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VXI Technology, Inc.
98 VM1548C Theory Of Operation
VXI I
NTERFACE
D
EVICE
T
RANSFERS
(W
RITE
M
ODE
)
When write transfers to the UUT are selected, the VM1548C will select the direction of the
transfer, enable the clocks for the selected channel(s), latch the data into the I/O word buffer and
clock the I/O data buffer using the appropriate triggering method.
D
IRECTION
Direction of transfer is controlled either from the front panel connector or from the Direction
Control latch (see Figure 5-1). Upon receipt of the SCPI command for setting the direction, the
Timing and Control FPGA decodes the VMIP address and issues the DOE* signal to the
read/write data buffer. This allows the transceiver (Read/Write Data Buffer) to be configured to
write data when both signals are low. The Timing and Control FPGA then generates the
PORTENA* signal that provides a low signal to the Port Decoder. Address bits A0, A1, and A2
are decoded causing the Port Decoder to provide a low going edge clocking the Direction Control
latch. This octal D latch provides the direction signal OUTENA0 that is OR’ed with the
corresponding I/O signal from the front panel connector.
The front panel I/O signal is active low and is pulled to VCC through a 47 k
Ω resistor. The signal
is then inverted and routed to the OR gate. The result of OR’ing these two signals together
provides a high on the I/O Data Buffer direction enable lines GBA* and GAB. This signal is also
routed to the I/O Word Buffer output write enable line OEAB1. This is done to avoid
READ/WRITE contentions between the two buffers. The I/O buffers are now configured to drive
the data to the UUT or the write mode.
C
LOCK
E
NABLE
Output clock enabling is accomplished when the VMIP module receives the SCPI command for
output clock enable. The Timing and Control FPGA then decodes the address and control bits
from the VMIP bus and generates the DOE* signal to the Read/Write Data Buffer. The Timing
and Control FPGA generates PORTENA* enabling the Port Decoder as detailed previously. This
time the address bits decode to PORT1* clocking the Write Clock Enable latch. The output of this
latch, CLKOUTENA0, is routed to the I/O Data Buffer clock enable line SAB.