VXI Technology, Inc.
102
VM1548C Theory Of Operation
D
EVICE
T
RANSFERS
(R
EAD
M
ODE
)
When read transfers from the UUT are selected, the VM1548C will select the direction of the
transfer, enable the clocks for the selected channel(s), latch the data into the I/O Data Buffer, if
double buffering is selected, using the appropriate triggering method and clock the I/O Word
Buffer.
This clock, or trigger, can be from either a TTL trigger input, the front panel connector CLK
input, a word serial event, or a TTL trigger out. The front panel connector CLK input will be used
to trigger the latching of data into the I/O Data Buffer and then generate an Interrupt Request
(IRQ) to the slot 0 controller.
D
IRECTION
Direction of transfer is controlled either from the front panel connector or from the Direction
Control latch (see Figure 5-3). Upon receipt of the SCPI command, the Timing and Control FPGA
decodes the VMIP address and issues the DOE* signal to the Read/Write Data Buffer, allowing
the data on the inputs to be available on the outputs when both signals are low. The Timing and
Control FPGA then generates the PORTENA* signal that provides a low signal to the Port
Decoder. Address bits A0, A1 and A2 are decoded, causing the Port Decoder to provide a low
going edge clocking the Direction Control latch. This octal D latch provides the direction signal
OUTENA0, a low equates to read and a high equates to write. This, then, is OR’ed with the
corresponding I/O signal from the front panel connector.
The front panel connector I/O signal is active low and is pulled to VCC through a 47 k
Ω
resistor.
The signal is then inverted and routed to the OR gate. The result of OR’ing these two signals
together provides a low on I/O Data Buffer direction enable lines GBA* and GAB. This signal is
also routed to the I/O Word Buffer output write enable line OEAB1. This is done to avoid
READ/WRITE contentions between the two buffers. The I/O buffers are now configured to
receive data from the UUT or the read mode.
C
LOCK
E
NABLE
Input clock enabling is accomplished when the VMIP module receives the SCPI command for
input clock enable. The Timing and Control FPGA then decodes the address and control bits from
the VMIP bus and generates the DOE* signal to the Read/Write Data Buffer. The Timing and
Control FPGA generates PORTENA* enabling the Port Decoder as detailed previously. This time
the address bits decode to PORT0* clocking the Read Clock Enable latch. The output of this latch
CLKINENA0 is routed to the I/O Data Buffer clock enable line SBA. Loading of data into the I/O
Data Buffer occurs when the VM1548C receives the appropriate input clock or trigger as
specified by the SCPI command.
