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VXI Technology VM1548C, User Manual

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VXI Technology VM1548C User Manual Download Page 33

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VM1548C Programming 

33 

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In this example, a wrap-around cable will be used to configure and transfer data from port 0, 
port 1, and port 2 to port 3, port 4, and port 5. The wrap-around cable pin outs used are as defined 
in Table 3-1. The data to be sent is port 0 = 01, port 1 = 23, and port 2 = 45. The IRQ* signal will 
be generated from the external clock received from port 5. 
 

COMMANDS DESCRIPTION 

INP:REG:SOUR 3 EXT

 

Selects External clock line as the clock source for 
port 3 

INP:REG:POL 3 INV

 

Selects the inverted (falling) clock edge for port 3 

INP:REG:SOUR 4 EXT

 

Selects External clock line as the clock source for 
port 4 

INP:REG:POL 4 INV

 

Selects the inverted (falling) clock edge for port 4 

 

INP:REG:SOUR 5 EXT

 

Selects External clock line as the clock source for 
port 5 

INP:REG:POL 5 INV

 

Selects the inverted (falling) clock edge for port 5

 

OUTP:CLOC:ENAB 0 ON

 

Enables the output clock for port 0 

OUTP:CLOC:SOUR 0 IMM

 

Selects the IMM (word serial event) to  drive the 
external clock for port 0 

OUTP:REG:SOUR 0 IMM

 

Selects the IMM (word serial event) as the clock 
source for port 0 I/O data buffers

 

OUTP:CLOC:ENAB 1 ON

 

Enables the output clock for port 1 

OUTP:CLOC:SOUR 1 IMM

 

Selects the IMM (word serial event) to drive the 
external clock for port 1 

OUTP:REG:SOUR 1 IMM

 

Selects the IMM (word serial event) as the clock 
source for port 1 I/O data buffers 

OUTP:CLOC:ENAB 2 ON

 

Enables the output clock for port 1 

OUTP:CLOC:SOUR 2 IMM

 

Selects the IMM (word serial event) to drive the 
external clock for port 1 

OUTP:REG:SOUR 2 IMM

 

Selects the IMM (word serial event) as the clock 
source for port 1 I/O data buffers 

SOUR:DATA:ENAB 0 ON

 

Configures port 0 I/O data buffers for write mode 

SOUR:DATA:ENAB 1 ON

  

Configures port 1 I/O data buffers for write mode 

SOUR:DATA:ENAB 2 ON

 

Configures port 2 I/O data buffers for write mode 

SOUR:DATA:ENAB 3 OFF

 

Configures port 3 I/O data buffers for read mode 

SOUR:DATA:ENAB 4 OFF

 

Configures port 4 I/O data buffers for read mode 

SOUR:DATA:ENAB 5 OFF

 

Configures port 5 I/O data buffers for read mode

 

SOUR:DATA 0 01

 

Writes data “01” to port 0’s I/O data buffer

 

SOUR:DATA 1 23

 

Writes data “23” to port 1’s I/O data buffer

 

SOUR:DATA 2 45

 

Writes data “45” to port 2’s I/O data buffer

 

STAT:INT:ENAB EXT 5

 

Set the interrupt trigger source as the port 5 clock

 

STAT:INT:PTR ON

 

Set the interrupt trigger source to the positive edge

 

TRIG:SEQ:IMM

 

Generates a word serial event to transfer data and 
clocks from ports 0, 1, and 2

 

READ? 3

 

Read data from port 3

 

READ? 4

 

Read data from port 4

 

READ? 5

 

Read data from port 5

 

 
See Figure 3-3 for the Write/read block diagram. 

Summary of Contents for VM1548C

Page 1: ...bus VM1548C TTL I O MODULE USER S MANUAL P N 82 0045 000 Released July 31 2007 VXI Technology Inc 2031 Main Street Irvine CA 92614 6509 949 955 1894...

Page 2: ...2...

Page 3: ...rements 17 Setting the Chassis Backplane Jumpers 17 Setting the Logical Address 18 Front Panel Interface Wiring 19 SECTION 3 20 PROGRAMMING 20 Introduction 20 Notation 22 EXAMPLES OF SCPI COMMANDS 23...

Page 4: ...Nse 79 SOURce DATA 80 SOURce DATA ENABle 81 SOURce DATA POLarity 82 STATus INTerrupt ENABle 83 STATus INTerrupt NTRansition 84 STATus INTerrupt PTRansition 85 TRIGger SEQuence IMMediate 86 SCPI REQUIR...

Page 5: ...www vxitech com VM1548C Preface 5 Clock Enable 102 Latch Data 103 Read Data 104 INDEX 105...

Page 6: ...es duties and taxes for products returned to VTI from another country VTI warrants that its software and firmware designated by VTI for use with a product will execute its programming when properly in...

Page 7: ...nclusive 93 68 EEC and carries the CE mark accordingly The product has been designed and manufactured according to the following specifications SAFETY EN61010 2001 EMC EN61326 1997 w A1 98 Class A CIS...

Page 8: ...r loss of data These symbols may appear on the product ATTENTION Important safety instructions Frame or chassis ground Indicates that the product was manufactured after August 13 2005 This mark is pla...

Page 9: ...ctric shock the grounding conductor must be connected to earth ground Operating Conditions To avoid injury electric shock or fire hazard Do not operate in wet or damp conditions Do not operate in an e...

Page 10: ...949 955 1894 Fax 949 955 3041 VXI Technology Cleveland Instrument Division 5425 Warner Road Suite 13 Valley View OH 44125 Phone 216 447 8950 Fax 216 447 8951 VXI Technology Lake Stevens Instrument Di...

Page 11: ...vailable as a 48 96 or 144 channel singlewide VXIbus instrument Figure 1 1 and Figure 1 2 show the 144 channel version of the VM1548C The 96 channel version would not have J200 and its associated LED...

Page 12: ...VXI A16 registers Group wise programmable polarity through VXI A16 registers as an active high or low Input 0 V to 60 V VIN high 2 0 V VIN low 1 5 V input impedance 65 k Output Open collector N DMOS...

Page 13: ...ollect or present data to a UUT unit under test Each clock input is internally pulled to a logic high level and has a RC termination network to reduce multiple clocking due to line ringing The RC netw...

Page 14: ...3 1 MUX 22 120 47K 100pF 47K I O DATA I O WRITE DATA VMIP BUS VXI BACKPLANE TTL TIGGER 0 7 TTL TRIGGER SELECT READ DATA TTL TRIG OUT SEL CLKOUTENA CLK IN SEL CLK OUT SEL CLKINENA A B A B D Q D Q Q D...

Page 15: ...ge divider and voltage comparator on the input side CHANNEL INPUT CHARACTERISTICS VIN high VIN low VIN max Input Impedance 2 0 V 1 5 V 60 V 65 k CHANEL OUTPUT CHARACTERISTICS VOUT max Current Sink Max...

Page 16: ...VXI Technology Inc 16 VM1548C Introduction...

Page 17: ...SYSTEM POWER AND COOLING REQUIREMENTS The power and cooling requirements of the VM4018 are given in the Specifications section of Section 1 in this manual It is imperative that the chassis provide ad...

Page 18: ...ical addresses as required by the VXIbus specification revisions 1 3 and 1 4 The logical address of the instrument is set on the VMIP carrier The VMIP logical addresses must be set to an even multiple...

Page 19: ...le from a variety of sources The connector attaches to two 34 conductor 0 050 centers ribbon cable and the pin out has been selected to allow for using the twisted pair type of ribbon cable Some manuf...

Page 20: ...it Assembly P N CA 68NDP 12GT Connector P N CA 68NDBS 1M Back Shell P N DG01 Catalog covering this series of connectors The pin locations for J200 J201 and J202 are shown in Figure 2 2 PIN 1 PIN 35 PI...

Page 21: ...in upper and lower case Character case is used to indicate different forms of the same command Keywords can have both a short form and a long form some commands only have one form The short form uses...

Page 22: ...form of the command generally replaces the parameter with a question mark Query responses do not include the command header This means only the parameter is returned no part of the command or question...

Page 23: ...TLTrig n Where n refers to one of the 8 TTLTRIG lines The TTLTRIGGER is enabled or disabled using the following SCPI command OUTPut TTLTrig STATe ON Enables the Trigger OUTPut TTLTrig STATe OFF Disabl...

Page 24: ...mand will trigger the status interrupt on a positive edge STATus INTerrupt PTRansition ON The following SCPI command will trigger the status interrupt on a negative edge STATus INTerrupt NTRansition O...

Page 25: ...is transparent EXAMPLES The following SCPI commands will clock the number 205 out of port 5 using the IMMEDIATE pulse SOURce DATA ENABle 5 ON OUTPut REGister SOURce 5 IMMEDIATE SOURce DATA 5 205 TRIGg...

Page 26: ...is INPut REGister SOURce port NONE Where port is 1 of 6 data registers and NONE means this data register is transparent EXAMPLES The following SCPI commands will clock the data in on port 3 using the...

Page 27: ...an input OUTPut CLOCk ENABle OFF When the circuit is operating as an output the clock source is selectable using the following SCPI command OUTPut CLOCk SOURce port source Where source is TTLTRIG IMME...

Page 28: ...he clock input to port 0 OUTP CLOC ENAB 1 0 Same as previous command except for port 1 OUTP REG SOUR 0 EXT Selects port 0 input clock CLK0 as method of triggering OUTP REG SOUR 1 EXT Same as previous...

Page 29: ...control circuitry that the front panel clock lines are used as inputs This allows the UUT to furnish the clock source when ready to receive data The OUTP REG SOUR 0 EXT and the OUTP REG SOUR 1 EXT com...

Page 30: ...t is generated from the VM1548C The VM1548C will capture or read data on the falling edge of this same clock When the VM1548C detects a TTL Trigger 1 the front panel clock lines to the UUT are activat...

Page 31: ...ol Trigger Select Input Data Buffers ports 3 4 5 I O Word Buffer Port Decoder Read Write Data Buffer Trigger In Mux 120 22 47K 100pF VCC CLKIO port to front panel CLKIN port 22 Data Bus Read Read port...

Page 32: ...select TTL trigger 1 for the clock source The port decoder is again enabled to clock the trigger select latch selecting the TINSEL signals These signals are routed to the trigger in mux that enables T...

Page 33: ...cts the IMM word serial event to drive the external clock for port 1 OUTP REG SOUR 1 IMM Selects the IMM word serial event as the clock source for port 1 I O data buffers OUTP CLOC ENAB 2 ON Enables t...

Page 34: ...ort CLKOUT port PORT3 WRITE0 CLKOUT port IN OUT port READ READ port CLKIN port CLOCK0 PORTENA TINENA TINSEL0 1 2 FIGURE 3 3 WRITE READ The INP REG SOUR port EXT commands select the external clock for...

Page 35: ...atch selecting the CLKOUTENA The CLKOUTENA signals are applied to the I O data and word buffers enabling the output clock line The SOUR DATA ENAB port ON enables the selected ports for a write in this...

Page 36: ...ATA3 7 43 I O 0 10 I O 3 44 CLK0 11 CLK3 45 DATA1 0 13 DATA4 0 47 DATA1 1 14 DATA4 1 48 DATA1 2 15 DATA4 2 49 DATA1 3 16 DATA4 3 50 DATA1 4 17 DATA4 4 51 DATA1 5 18 DATA4 5 52 DATA1 6 19 DATA4 6 53 DA...

Page 37: ...ion used to read the register performs 16 bit reads Example 1 For example in order program Port 1 a First the register value at offset 0x20 is read Assume that the value read is as given below 1111000...

Page 38: ...owing diagram shows A16 Memory and the Model VM1548C Data Port Map TABLE 3 2 A16 MEMORY MAP Offset Register 3E 3C 3A 38 36 34 32 30 2E Event R W 2C Source Data Polarity R W 2A Clear ISENSE R W 28 IPIN...

Page 39: ...8_PORT_TWO Port Two vtvm1548_PORT_THREE Port Three vtvm1548_PORT_FOUR Port Four vtvm1548_PORT_FIVE Port Five ViInt16 clkSource This parameter is used to set the source of the clock circuit associated...

Page 40: ...e specified port as output and write the specified data value to it It then triggers the port to output its data ViStatus _VI_FUNC vtvm1548_setupAndWriteData ViSession instrHndl ViInt16 portNumber ViI...

Page 41: ...eters ViSession instrHndl A valid session handle to the instrument ViInt16 portNumber This parameter is used to specify the port which is to be configured as input Valid Values Interpretation vtvm1548...

Page 42: ...ified input port Return Values Returns VI_SUCCESS if successful Else returns error value Description This function is an application function that shows how the user can use core functions to set up t...

Page 43: ...mber vtvm1548_CLK_SOURCE_IMM VI_NULL if status VI_SUCCESS return vtvm1548_ERROR_SETTING_REGISTER Trigger the input port using the IMMEDIATE pulse status vtvm1548_triggerSeqImmediate instrHndl if statu...

Page 44: ...VXI Technology Inc 44 VM1548C Programming...

Page 45: ...r page in detail The description is presented in a regular and orthogonal way assisting the user in the use of each command Every command entry describes the exact command and query syntax the use and...

Page 46: ...d of operation of a port The data will be latched out or in with reference to a clock source Transparent Mode This refers to the method of operation of a port For example if the port is being used as...

Page 47: ...t Status Enable Register X ESR Queries the Standard Event Status Register IDN Query the module Identification string OPC Set the OPC bit in the Event Status Register RST Resets the module to a known s...

Page 48: ...specified port X Disabled OUTPut TTLTrig Selects 1 of 8 VXI Trigger lines as the output trigger X 0 OUTPut TTLTrig POLarity Sets the active edge of the TTL trigger X NORMal OUTPut TTLTrig SOURce Sele...

Page 49: ...ion ENABle Sets the Operation Status Enable Register X 0 STATus QUEStionable EVENt Queries the Questionable Status Event Register N A STATus QUEStionable CONDition Queries the Questionable Status Cond...

Page 50: ...legal range Reset Value Describes the values assumed when the RST command is sent Query Syntax Details the exact query form of the command Query Parameters Describes the parameters sent with the comm...

Page 51: ...88 2 Common Command Command Syntax CLS Command Parameters None RST Value N A Query Syntax None Query Parameters N A Query Response N A Description This command clears all event registers clears the OP...

Page 52: ...ister A value of 1 in a bit position of the ESE register enables generation of the ESB Event Status Bit in the Status Byte by the corresponding bit in the ESR If the ESB is set in the ESR register the...

Page 53: ...quest not used in the VM1548C always 0 Bit 7 Power On The Operation Complete bit is set when it receives an OPC command The Query Error bit is set when data is over written in the output queue This co...

Page 54: ...ring of the VM1548C module The response is divided into four fields separated by commas The first field is the manufacturer s name the second field is the model number the third field is an optional s...

Page 55: ...Value N A Query Syntax OPC Query Parameters None Query Response 1 Description The Operation Complete command sets the OPC bit in the Event Status Register when all pending operations have completed T...

Page 56: ...T Command Parameters None RST Value N A Query Syntax None Query Parameters N A Query Response N A Description The Reset command resets the module s hardware and software to a known state See the comma...

Page 57: ...on The Read Status Byte query fetches the current contents of the Status Byte Register See the IEEE 488 2 specification for additional information regarding the Status byte Register and its use The la...

Page 58: ...Command Command Syntax TRG Command Parameters None RST Value N A Query Syntax None Query Parameters N A Query Response N A Description This command generates a short pulse or a word serial event for...

Page 59: ...2 Common Command Command Syntax None query only Command Parameters N A RST Value N A Query Syntax TST Query Parameters None Query Response Numeric value Description The Self Test query causes the VM15...

Page 60: ...T Value N A Query Syntax None Query Parameters N A Query Response N A Description The Wait to Continue command halts the execution of commands and queries until the No Operation Pending message is tru...

Page 61: ...ata from the instrument This command applies only to the SOURce DATA and READ commands ASCii Specifies numbers expressed in decimal Leading zeros are suppressed HEXadecimal Expresses numbers in a 2 di...

Page 62: ...port 0 1 2 3 4 5 Query Response NORM INV Description A Polarity of NORMal would cause the data to be latched in on a rising edge of the clock A Polarity of INVert would cause the data to be latched i...

Page 63: ...pecified port s input clock Source Parameter Description NONE This disables the specified port s input clock The data appearing on the specified port is read without any latching TTLTrig This selects...

Page 64: ...0 Query Syntax INPut TTLTrig Query Parameters N A Query Response Numeric ASCII value between 0 and 7 Description The Input TTLTrig command controls which of the 8 VXI trigger lines will be selected a...

Page 65: ...INPut TTLTrig STATE boolean Command Parameters boolean 0 1 OFF ON RST Value 0 Query Syntax INPut TTLTrig STATE Query Parameters N A Query Response 0 1 Description The Input TTLTrig state command enab...

Page 66: ...rs port 0 1 2 3 4 5 Query Response 0 1 Description The output clock enable command determines which direction the associated port s external clock line will be driven This clock line is a pin on the 6...

Page 67: ...ontrols the polarity of the specified port s external clock line There are six individual clock circuits see clock circuit description A polarity of NORMal will produce a rising edge clock on the 68 p...

Page 68: ...mmand selects a signal to be used as the source for the output clock appearing on the 68 pin external connector Source Parameter Description NONE This parameter will select GROUND as the clock source...

Page 69: ...ption The Output Register Polarity command controls the polarity at which output data is latched to the specified port A polarity of NORMal would cause the data to be latched out on a rising edge of t...

Page 70: ...e specified port s output clock The data appearing on the specified port will latch out immediately TTLTrig This selects the VXIbus TRIGIN as the clock source TRIGIN can be 1 of 8 trigger lines on the...

Page 71: ...d Parameters n 0 1 2 3 4 5 6 7 RST Value 0 Query Syntax OUTPut TTLTrig Query Parameters N A Query Response 0 1 2 3 4 5 Description The Output TTLTrig command controls which of the 8 VXI trigger lines...

Page 72: ...polarity command controls the polarity of the TTL TRIGGER signal driving the VXI trigger line When polarity is NORMal the selected VXIbus trigger line will provide a rising edge trigger When polarity...

Page 73: ...as the TRIGOUT signal The TRIGOUT signal is referred to throughout this manual as GLOBAL Source Parameter Description EXTernal0 5 Selects one of the six external clocks as TRIGOUT See the clock circui...

Page 74: ...an Command Parameters boolean 0 1 OFF ON RST Value 0 Query Syntax OUTPut TTLTrig STATE Query Parameters N A Query Response 0 1 Description The Output TTLTrig State command enables or disables the sele...

Page 75: ...ion this command is a query and will respond with the value read from the data register The format of the returned data is set with the FORMat command This command requires that the register be enable...

Page 76: ...Parameters N A Query Response 0 to 63 decimal Description The Read Clocks command queries and returns the clock line levels The 6 bit response signifies a high or low on each clock line 0 through 5 Ex...

Page 77: ...5 are accessed from the front panel These signals are normally pulled high The user has the option of setting SOURce DATA ENABle to 0 or OFF which is the default and controlling the ports as inputs or...

Page 78: ...t response signifies a high or low on each 6 line grouping Each 6 line grouping corresponds with one hardware driver chip An over current condition occurs when the combined current through the six lin...

Page 79: ...Parameters N A Query Response N A Description The Reset ISense command resets drive disable in a group of six lines after an over current condition is cleared Each bit corresponds to a group of six li...

Page 80: ...riven The format of the returned information is determined by the FORMat command Query Parameters port 0 1 2 3 4 5 Query Response 0 255 Description The Source Data command will write an 8 bit value to...

Page 81: ...5 boolean 0 1 OF ON RST Value 0 Query Syntax SOURce DATA ENABle port Query Parameters port 0 1 2 3 4 5 Query Response 0 1 Description The Source Data Enable command controls the direction of the I O d...

Page 82: ...3 4 5 NORMal 1 in 1 out INVert 1 in 0 out RST Value NORMal on all ports Query Syntax SOURce DATA POLarity port Query Parameters port 0 1 2 3 4 5 Query Response NORM INV Description The Source Data Pol...

Page 83: ...EXT n GLOB NONE Description The Status Interrupt enable command selects a source for the interrupt trigger Source Parameter Description EXT 0 5 This selects 1 of 6 external clocks See the clock circu...

Page 84: ...n on which the interrupt trigger will occur If the negative transition is set to on then a falling edge trigger will generate an interrupt If the negative transition is off then a rising edge trigger...

Page 85: ...n on which the interrupt trigger will occur If the positive transition is set to on then a rising edge trigger will generate an interrupt If the positive transition is off then a falling edge trigger...

Page 86: ...pulse Type Event Command Syntax TRIGger SEQuence IMMediate Command Parameters None RST Value N A Query Syntax None Query Parameters N A Query Response N A Description This command generates a short pu...

Page 87: ...ax None query only Command Parameters N A RST Value N A Query Syntax STATus OPERation EVENt Query Parameters None Query Response 0 Description The Status Operation Event Register query is included for...

Page 88: ...Command Parameters N A RST Value N A Query Syntax STATus OPERation CONDition Query Parameters None Query Response 0 Description The Operation Status Condition Register query is provided for SCPI compl...

Page 89: ...Query Parameters None Query Response Numeric ASCII value from 0 to 32767 Description The Operation Status Enable Register is included for SCPI compatibility and the VM1548C does not alter any of the...

Page 90: ...ed SCPI command Command Syntax STATus PRESet Command Parameters None RST Value N A Query Syntax None command only Query Parameters N A Query Response N A Description The Status Preset command enables...

Page 91: ...t condition 1 over current condition Description The Questionable Status Condition Register query returns one bit that indicates what the over current sense condition is A 1 signifies there is an over...

Page 92: ...plied Query Syntax STATus QUEStionable ENABle Query Parameters None Query Response Numeric ASCII value from 0 to 32767 Description The Status Questionable Enable command sets the bits in the Questiona...

Page 93: ...nd Parameters N A RST Value N A Query Syntax STATus QUEStionable EVENt Query Parameters None Query Response 0 no over current condition 1 over current condition Description The Questionable Status Eve...

Page 94: ...error queue The error queue will maintain the two error messages If additional errors occur the queue will overflow and the second and subsequent error messages will be lost In the case of an overflow...

Page 95: ...command Command Syntax None query only Command Parameters N A RST Value N A Query Syntax SYSTem VERSion Query Parameters None Query Response Numeric ASCII value Description The System Version query r...

Page 96: ...VXI Technology Inc 96 VM1548C Command Dictionary...

Page 97: ...data words to be transmitted or received The VM1548C contains the capability to generate a TTL trigger onto the VXI backplane using a word serial event one of six front panel clock inputs or from a TT...

Page 98: ...Control latch This octal D latch provides the direction signal OUTENA0 that is OR ed with the corresponding I O signal from the front panel connector The front panel I O signal is active low and is pu...

Page 99: ...o the selected I O Word Buffer thus latching the data The I O buffers are enabled and configured to transmit data from channel 0 to the UUT upon receipt of the proper clock or trigger VMIP Bus Timing...

Page 100: ...causing the Port Decoder to provide a low going edge clocking the Trigger Select latch The Trigger Select latch then outputs the binary equivalent number that matches the desired trigger and the trig...

Page 101: ...Control Trigger Select I O Data Buffer I O Word Buffer Port Decoder Read Write Data Buffer Trigger In Mux 22 TRIGIN0 7 TRIGIN TINENA TINSEL0 1 2 CLKOUT0 PORT3 D8 D15 CLKOUT0 Data Bus Data Bus Data Bus...

Page 102: ...de a low going edge clocking the Direction Control latch This octal D latch provides the direction signal OUTENA0 a low equates to read and a high equates to write This then is OR ed with the correspo...

Page 103: ...and a 47 k resistor to VCC This termination value gives a time constant of 12 ns for fast rise times on input clocks and will not load the UUT driving source The received clock now referred to as CLOC...

Page 104: ...ta Buffer The Timing and Control FPGA then issues the READ signal to the previously enabled I O Word Buffer thus latching the data The Timing and Control FPGA generates the DOE signal to the Read Writ...

Page 105: ...ENABle 66 OUTPut CLOCk POLarity 67 OUTPut CLOCk SOURce 68 OUTPut REGister POLarity 69 OUTPut REGister SOURce 70 OUTPut TTLTrig 71 OUTPut TTLTrig POLarity 72 OUTPut TTLTrig SOURce 73 OUTPut TTLTrig ST...

Page 106: ...VXI Technology Inc 106 VM1548 Index V VMIP 11 12 30 97 98 102 104 VXI 11 30 32 38 97 98 100 103 104 VXI message based interface 13 VXIbus 21 W WEEE 8 Write mode 28 Write read mode 33...

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