VXI Technology, Inc.
104
VM1548C Theory Of Operation
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Upon receipt of the SCPI command to read the data, the Timing and Control FPGA decodes the
address and control bits from the VMIP bus and generates the READ0* signal to the OEBA1
input of the I/O Word Buffer. This enables the I/O Word Buffer to input data from the I/O Data
Buffer.
The Timing and Control FPGA then issues the READ signal to the previously enabled I/O Word
Buffer thus latching the data. The Timing and Control FPGA generates the DOE* signal to the
Read/Write Data Buffer. This allows the input data from the UUT to be available on the VXI data
bus.
Note that data inputs to the module do not contain pull-up or down-biasing resistors. If the user
does not provide active or passive biasing of the data inputs, a read of the port may result in either
a “1” or “0” being read from the data inputs.
