VXI Technology VM1548C, User Manual

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VXI Technology, Inc.
100 VM1548C Theory Of Operation
D
EVICE
T
RIGGERING
(TTL I
NPUT
T
RIGGER
)
The VM1548C is capable of both receiving and generating VXI TTL triggers. The generated TTL
triggers may be used to signal another VXI instrument that a VM1548C event has occurred. The
VM1548C can also receive any one of eight TTL triggers from the VXI backplane, TTL trigout,
or a front panel connector clock line for use in triggering all six channels at once.
T
RIGGER
D
ECODE
Upon receipt of the command that informs the Timing and Control FPGA that the input trigger
feature has been selected. The Timing and Control FPGA generates the PORTENA* signal that
provides a low signal to the Port Decoder (see Figure 5-2). Address bits A0, A1, and A2 are
decoded causing the Port Decoder to provide a low going edge clocking the Trigger Select latch.
The Trigger Select latch then outputs the binary equivalent number that matches the desired
trigger and the trigger input enable signal TINENA*.
T
RIGGER
S
ELECT
The select lines TINSEL0, TINSEL1, TINSEL2 and enable signal TINENA* are then routed to
the Trigger Input Mux. This 8:1 mux will select the desired trigger. The output of the Trigger
Input Mux is the signal TRIGIN* and is routed to the Timing and Control FPGA. Once inside the
Timing and Control FPGA, the TRIGIN* signal may be inverted to produce a falling edge if this
feature has been selected or remain in the normal default state of a rising edge. The signal is then
muxed to the output clock circuitry in the Timing and Control FPGA and routed to the selected
I/O Data Buffer as CLKOUT0. The rising edge of this signal then clocks the I/O Data Buffer to
drive the I/O data outputs onto the UUT.