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EX1629 Programming
81
Sample Code
ViStatus result = VI_SUCCESS;
/* Configure the system to acquire 100 samples. */
result = vtex1629_set_sample_count( vi, 0, 100 );
/* Reset the trigger system to return the trigger bus to its default
configuration. */
result = vtex1629_reset_trigger_arm( vi );
/* Set the sample clock source as a standalone device using the
dedicated sample clock line. */
result = vtex1629_set_sample_clock_source( vi,
VTEX1629_SAMP_CLK_MODE_MASTER,
VTEX1629_LXI_LINE_NONE,
VTEX1629_LXI_LINE_NONE);
/* Set the synch source as a standalone device using the dedicated
synch line. */
result = vtex1629_set_synch_source( vi,
VTEX1629_SYNC_MODE_MASTER,
VTEX1629_LXI_LINE_NONE,
VTEX1629_LXI_LINE_NONE);
/* Set the arm source to immediate ARM. */
result = vtex1629_set_arm_source( vi, VTEX1629_TRIG_SRC_IMMEDIATE);
/* Set the trigger source to immediate trigger. */
result = vtex1629_set_trigger_source( vi,
VTEX1629_TRIG_SRC_IMMEDIATE);
/* Issue a synchronization signal since the sample clock source was
changed. */
result = vtex1629_soft_synch( vi );
Multiple Instruments (Master/Slave) Example Configuration
The Master/Slave configuration is suitable for larger acquisition systems, up to several thousand
channels (hundreds of instruments). By sharing a single oscillator and utilizing a synchronization
signal from the master, the acquisition of all instruments can be coordinated and phase aligned.
One instrument is assigned the role of “master” and its internal oscillator and synchronization
signals are routed externally via the LXI Trigger Bus. The remaining “slave” instruments are
configured to accept the external clock and synchronization signals from the LXI Trigger Bus.
Through the proper sequencing of instrument driver calls, and the resultant hardware events and
signals, the ensemble of instruments can be made to behave as one large acquisition system, as
illustrated by the sample code below. The following code:
Sets the number of samples to acquire on a trigger to 100 (one second’s worth with the
100 Sa/s sample rate)
Properly configures the LXI Trigger Bus and DIO banks
Sets the ADC clock to master/slave on LXI 0
Sets ADC synchronization to master/slave on LXI 1
Configures a timer trigger on LXI 2
Configures a pattern arm on LXI 3
