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EX1629 Programming
79
To allow added flexibility for more complicated multi-box configurations, the sample clock can
also be output on one trigger bus line and input on another. This functionality is useful in star
multi-box configurations. For example, the master device can be configured to output the clock on
LXI0. A trigger bus hub can be utilized to receive this clock on LXI0 and distribute it to the
master and slave devices on LXI4. The master device can then be configured to receive its clock
on LXI4 instead of using the clock that it is outputting on LXI0. This allows the master and slave
devices to use the same clock from the trigger bus hub instead of the master using one clock and
the slaves using the same clock but with the added phase delay of the trigger bus hub.
The vtex1629_set_sample_clock_source instrument driver function is used to configure the
sample clock source. For a master or standalone device, the
sampleClockMode
parameter should
be set to VTEX1629_SAMP_CLK_MODE_MASTER. The
outLine
parameter specifies the
trigger bus line that is used to output the clock. This can be either one of the trigger bus lines or
can be set to VTEX_LXI_LINE_NONE to use the internal sample clock line. The
inLine
parameter specifies what line is used by the device for its ADC clock. This may or may not be the
same as the lines that is specified to output the clock via the outLine parameter. As with the
outLine
parameter, specifying an input line of VTEX_LXI_LINE_NONE will instruct the device
to use the internal sample clock line. In the case of a stand alone device that uses the internal
sample clock line, both the input and the output lines are set to VTEX_LXI_LINE_NONE.
If a trigger bus line will be used for distributing the sample clock or for receiving a clock back into
the device from an external source, it must be configured prior to configuring the sample clock.
Regardless of whether the sample clock is only used within the device or if it is distributed to
other devices, the trigger bus line that is used to output the sample clock (specified by the
outLine
parameter) must be configured as an output using the vtex1629_set_lxibus_configuration function.
If this line will only be used within the device, the transmission scope for the line should be set to
internal transmission only. If the sample clock output is intended to be driven out on the external
trigger bus, the transmission scope must be set for external and internal transmission. If the sample
clock is input on different trigger bus line than it is output, the input trigger bus line must be
configured as an input with external and internal transmission scope using the
vtex1629_set_lxibus_configuration function. When the internal sample clock line is used,
configuration of the trigger bus lines is not required.
Sample clock configuration on a slave device is much simpler than that of a master device. The
vtex1629_set_sample_clock_source function is used to specify a
sampleClockMode
parameter of
VTEX1629_SAMP_CLK_MODE_SLAVE as well as indicating the trigger bus line that will be
used to receive the sample clock. The trigger bus line must be configured as an input with external
and internal transmission scope.
ADC Synchronization
Configuration of the ADC synchronization signal is similar to configuration of the ADC sample
clock. Standalone and master devices are similar in that they are both configured with a
syncMode
parameter of VTEX1629_SYNC_MODE_MASTER using the vtex1629_set_synch_source
function. As a standalone or master device, synchronization pulses are generated on the specified
synchronization signal line using the vtex1629_soft_synch function. The
outLine
parameter for
this function is used to specify which trigger bus line is used to output the synchronization signal.
It can either specify one of the trigger bus lines or a dedicated internal synchronization signal line.
As with the ADC sample clock source, the synchronization signal can be configured to only be
used within the device or to be output to other devices using the external trigger bus. To allow
flexibility, the synchronization signal can be received back into the device on a different line than
the one on which it is output. As with the ADC sample clock, any trigger bus lines that are used
for the synchronization signal must be properly configured as inputs or outputs and with the
proper transmission scope before they can be used for the synchronization signal. For a standalone
device, the synchronization signal is typically configured to use the internal dedicated
synchronization
signal
line
by
setting
both
the
input
and
output
lines
to
VTEX1629_LXI_LINE_NONE.
