VTI Instruments Corp.
APPENDIX B
86
A
PPENDIX
A
D
IGITAL
A
NTI
-
ALIAS
F
ILTER AND
M
EASUREMENT
S
PAN
O
VERVIEW
The EMX-4250/4350/4380 uses analog-to-digital converter (ADC) based on delta-sigma
architecture. The analog signal is first filtered by an analog anti-aliasing filter at a fixed corner
frequency (see
Anti-Alias Filter
in page 71) to attenuate signals with frequencies close to the delta-
sigma converter oversampling clock frequency. The digitized signal is filtered by a digital FIR filter
in the ADC chip for the highest span data. For lower span (sample rate) data, signal is further filtered
by up to sixteen stages of digital decimation filters to avoid aliasing error.
The EMX-4250/4350/4380 implements ÷2 decimation filters along with an optional ÷5 decimation
filter. These filters are linear phase FIR filter with very low pass-band ripple and high dynamic range
even after sixteen stages of filtering.
Figure A-5-1: ÷2 Decimation Filter
Figure A-5-2: ÷5 Decimation Filter
Span
Span
Sample Rate/2
Guard-band
