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APPENDIX D
113
S
YNCHRONIZATION
P
ERFORMANCE
Two histograms show typical synchronization error between two chassis using trigger cable, and
LAN event
3
. When the chassis are synchronized by dedicated cable, the error is mainly determined
by signal transmission delay caused by signal routing and cable length.
Figure E-1: Typical chass-to-chasss phase error (in degrees) at 1kHz
With LAN synchronization, unlike by cable, the error is usually distributed around zero. This is
because IEEE 1588 algorithm corrects for the time delay of LAN packet transmission between
master clock and slave. As far as the delay is equal for both directions, the average error becomes
zero. The error variance largely depends on the network configuration. The quality of network
switches, amount of network traffic, and the stability of master clock, greatly affect the actual
synchronization performance, or phase error. A dedicated network for the test system with a stable
GPS Grandmaster clock (PTP v2), connected with boundary/transparent clock switches
4
provides
the best and the most consistent performance.
3
The test result with Dell PowerConnect™ 2724 Gigabit Ethernet switch.
4
e.g., Meinberg LANTIME™, Hirschmann MACH1000™
