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Register Summary

– Register Descriptions

VL-586-1 Reference Manual

AP AND

AGING

ONTROL

EGISTER

MPCR (READ/WRITE) 00E3H

FPAGE

Reserved

RPG5

RPG4

RPG3

RPG2

RPG1

RPG0

Table 41: Map and Paging Control Register Bit Assignments

Bit

Mnemonic

Description

FPAGE

Flash Paging Enable

— Enables a 64K page frame from E0000h to EFFFFh.

Used to gain access to the on-board FLASH or BBSRAM.

FPAGE = 0

Page Frame Disabled.

FPAGE = 1

Page Frame Enabled.

—

Reserved

— This bit has no function. Always reads as 0.

D5-D0

RPG5-RPG0

Page Select

— Selects which 64K block is mapped into the page frame.

RPG5

RPG4

RPG3

RPG2

RPG1

RPG0

Memory Range

8 Pages BBSRAM

8 Pages FLASH 0

32 Pages FLASH 1

Summary of Contents for VL-586-1

Page 1: ...Reference Reference Reference Reference Manual Manual Manual Manual VL 586 1 5x86 Industrial CPU Card for the STD 32 Bus TM ...

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Page 3: ...VL 586 1 5x86 Industrial CPU Card for the STD 32 Bus TM M586 1 ...

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Page 5: ...000 All Rights Reserved Notice Although every effort has been made to ensure this document is error free VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose VersaLogic reserves the right to revise this product and associated documentation at any time without obligat...

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Page 7: ...echnical Specifications 4 Technical Support 5 Repair Service 5 2 DOS Based Quick Start 7 Introduction 7 Installation 8 Jumper Locations 9 Card Installation 10 Monitor Installation 11 Cable Installation 12 CMOS RAM Setup 12 CMOS Setup Options 13 Main CMOS Setup Menu 13 Basic CMOS Configuration 13 Advanced Configuration 13 Shadow Configuration 13 Reset CMOS to Last Known Values 13 Reset CMOS to Fact...

Page 8: ... Interrupt Configuration 32 Interrupt Configuration Jumpers 33 STD Bus Interrupt Signals 34 CPU Interrupt Request Inputs 35 Interprocessor Communications Interrupt Configuration 37 Non maskable Interrupt Configuration 37 4 Installation 39 Introduction 39 Card Insertion and Extraction 40 Card Installation 40 Card Placement 40 STD 80 Bus Installation Guidelines 40 STD 32 Bus Installation Guidelines ...

Page 9: ...OM1 Serial Port 54 COM2 Serial Port 54 LPT1 Parallel Port 55 Floppy Disk Drive Controller 56 IDE Hard Disk Drive Controller 56 Interrupt Controller Master 57 Interrupt Controller Slave 57 Counter Timers 58 Miscellaneous 58 Special Control Register 59 Watchdog Timer Hold Off Register 60 I O and Memory Map Control Register 61 Map and Paging Control Register 62 Appendix A Schematic 63 Index 72 ...

Page 10: ...ies Inc 408 434 0600 http www chips com 82C735 Super I O Chip Data Book STD 32 Manufacturers Group 800 733 2111 http www std32 com STD 32 Bus Specification and Designer s Guide Advanced Micro Devices 800 222 9323 http www amd com AM486DX5 133V17BHC Data Book Additional Resources http www annatechnology com http www annatech bookBrowseBySubjectF asp ...

Page 11: ...external connections Chapter 5 Register Descriptions Provides details about the user programmable registers on the CPU card Appendix A Schematics Circuit diagrams Introduction The VL 586 1 CPU card is fully PC hardware compatible and features a 32 bit 133 MHz Am5x86 microprocessor up to 32MB RAM 512K or 2 5MB Flash two COM ports one LPT port six counter timers and real time clock The card supports...

Page 12: ...odules are supported provided they are 70ns or faster Both 5V or 3 3V modules can be used jumper selectable BBSRAM The p version of the VL 586 1 includes 512K of on board Battery Backed Static RAM for non volatile storage of information This RAM is accessible through a 64K page frame at E0000h in the main memory map CMOS RAM Standard setup values are stored in a small battery backed CMOS RAM chip ...

Page 13: ...also contains 128 bytes of battery backed CMOS RAM with 114 bytes available as a system resource to store standard setup parameters Normally the BIOS requires 94 bytes leaving 20 bytes for general purpose use INTERRUPT CONTROLLERS Two PC AT compatible 8259 type programmable interrupt controllers PICs are provided for full DOS functionality Interrupt sources and destinations can be configured with ...

Page 14: ...es Output low voltage 0 5V 24 ma Output high voltage 2 4V 150 µA COM1 COM2 Serial Interfaces COM2 configurable as RS 232 422 485 Floppy Disk Drive Interface Supports two drives Hard Disk Drive Interface Supports two EIDE drives Memory Sockets DRAM 16 32 or 64 MB system dynamic RAM in one 72 pin SO DIMM gold plated socket SRAM battery backed on board 128K 512K byte battery backed static RAM in a JE...

Page 15: ...Quantity of items being returned The model and serial number of each item the serial number is a 5 digit bar code A description of the problem Steps you have taken to resolve or repeat the problem The return shipping address Warranty Repair All charges are covered including UPS 3rd Day Select shipping charges for return back to your facility Non warranty Repair All non warranty repairs are subject...

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Page 17: ... to boot The VL 586 1 includes a Flash Disk System and an installed bootable copy of Embedded DOS If you require a DR DOS disk call 1 541 485 8575 and we will send one free of charge The CMOS RAM information is shipped in its factory default condition which allows immediate booting to the command prompt If the CMOS Setup parameters need to be changed the most convenient method of setting up this i...

Page 18: ...ely sensitive to ESD and always require careful handling After removing the card from its protective wrapper or from the card cage place the card on a grounded static free surface component side up Use an anti static foam pad if available but not the card wrapper Do not slide the card over any surface The card should also protected during shipment or storage with anti static foam or bubble wrap To...

Page 19: ...Jumper Locations VL 586 1 Reference Manual DOS Based Quick Start 9 Jumper Locations Note Jumpers and resistor packs shown in as shipped configuration Figure 1 VL 586 1 CPU Card Layout ...

Page 20: ...e A VGA compatible monitor and a PC AT compatible keyboard are also required to complete the set of hardware necessary for development purposes Warning To prevent damage cards should be inserted in and removed from the card cage only when the system power is off Caution To avoid damaging cards they must be oriented correctly usually with the card ejector toward the top of the card cage Refer to th...

Page 21: ...tallation VL 586 1 Reference Manual DOS Based Quick Start 11 Monitor Installation A VGA monitor should be connected to the EPM SVGA module as shown Figure 2 Jumpers Connections for an EPM SVGA Using a VGA Monitor ...

Page 22: ...he configuration information is read by the CPU upon system reset The Setup program is permanently stored in ROM and can be run with or without an operating system present To run Setup reset the CPU card and press the DEL key when prompted Select BASIC CMOS CONFIGURATION to display a summary of the information stored in the CMOS RAM To change the values shown use the cursor arrows to move the high...

Page 23: ...OS ESC TO CONTINUE NO SAVE BASIC CMOS CONFIGURATION This option goes to another menu which allows you to change the following Date Time Drive assignments and types Boot sequence Keyboard Parameters Memory Tests ADVANCED CONFIGURATION This option goes to another menu which allows you to change the following Bus Timing Memory and I O Mapping Cache Control SHADOW CONFIGURATION This option allows you ...

Page 24: ... 104 Video Shadowing Enabled Advanced Configuration AT Bus Clock CPUCLK 4 Fast PC 104 Cycle Enabled DMA Clock AT Clk 2 Fast PCI Memory Cycle Enabled 16 bit PC 104 Wait States None CPU PCI Write Buffer Enabled PC 104 I O Recovery Enabled CPU PCI Write Buff Merge Enabled PC 104 I O Recovery Time 24 ATClk CPU PCI Write Buff Burst Enabled DRAM Read Timing Normal CPU PCI Fast Back to Back Enabled DRAM ...

Page 25: ...data Upon reset the CPU detects if the CMOS RAM is corrupted by analyzing the checksum If you wish to completely clear the contents of the CMOS RAM briefly move jumper V6 to position 1 2 top position then back to the position 2 3 lower position and reboot the system This process will load the factory default setup parameters into the CMOS RAM Warning Do not apply power to the CPU card with jumper ...

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Page 27: ...y on the card for various modes of operation The CMOS Setup configuration completes the process by establishing default operating conditions Hardware Jumper Summary Hardware option configuration is accomplished by installing or removing jumper plugs In this chapter the term in is used to indicate an installed jumper and out is used to indicate a removed jumper Use the following key to interpret th...

Page 28: ...Hardware Jumper Summary 18 Configuration VL 586 1 Reference Manual JUMPER BLOCK LOCATIONS Note Jumpers and resistor packs shown in as shipped configuration Figure 5 Jumper Block Locations ...

Page 29: ...rminated RS 485 intermediate multidrop stations only Out 28 V2 Counter Timer 5 Clock Source 250 kHz 1 MHz CTC 4 External Input 1 MHz V3 Counter Timer 4 Clock Source 250 kHz 1 MHz External Input 1 MHz V4 1 2 CMOS Battery Test Terminals Note V4 is not a jumper It is used as a test point to measure the current flowing in the CMOS battery circuit Do not place a jumper on these pins Out V5 1 2 Battery ...

Page 30: ...13 2 3 Interrupt Configuration IRQ10 Counter Timer 2 interconnect In Connects Counter Timer 2 Output to IRQ10 Out Disconnects CTC2 from IRQ10 Out 32 V14 1 2 Interrupt Configuration IRQ11 INTRQ2 interconnect In Connects STD Bus INTRQ2 P50 to IRQ11 Out Disconnects STD Bus INTRQ2 from IRQ11 In 32 V14 2 3 Interrupt Configuration IRQ11 Counter Timer 3 interconnect In Connects Counter Timer 3 Output to ...

Page 31: ...t In Connects STD Bus NMIRQ P46 to CPU NMI input Out CPU ignores activity on STD Bus NMIRQ P46 Out 30 V18 7 8 Permanent Temporary Master Selection In Permanent Master Mode V18 1 2 must be out RP15 RP22 must be in Out Temporary Master Mode RP15 RP22 must be out In 30 V19 1 2 General Purpose Digital Input In Causes bit D5 GP0 of the SCR register to read as 1 Out Causes bit D5 GP0 of the SCR register...

Page 32: ...re no configuration jumpers for the ROM sockets DRAM CONFIGURATION The on board DRAM socket U11 accepts one standard 72 pin SO DIMM module A variety of sizes may be used 16M 32M or 64M Fast Page Mode and EDO type modules are supported provided they are 70ns or faster and both 5V or 3 3V modules can be used The amount of memory is automatically determined by the BIOS when the system is reset The on...

Page 33: ...ock contents Out Normal operation V6 2 3 must be in Out V6 2 3 CMOS RAM Power In Connects power to CMOS RAM and Real Time Clock circuits Out Power disconnected In BATTERY BACKED SRAM CONFIGURATION Jumper V5 provides a means to disconnect power to the Battery Backed SRAM chip This jumper is for factory use only Table 6 CMOS RAM Jumpers Jumper Block Description As Shipped V5 1 2 Battery Backed SRAM ...

Page 34: ...IOS It always appears from 0F0000h to 0FFFFFh Bits D4 D0 in the MPCR register select which Flash ROM page is mapped into the 64K Page Frame 0E0000h to 0EFFFFh See IOMMAP and MPCR registers starting on page 61 for further information Two settings in the Advanced Configuration screen of the CMOS Setup menu control the memory region from C8000 to D7FFF and direct this area to the PC 104 or STD STD 32...

Page 35: ...ware should be written to communicate with the I O cards using the addresses listed above as X FF00h For example if your I O card is addressed at 38h the software should use FF38h as the I O port address USING 10 BIT STD BUS I O CARDS STD Bus I O cards which only decode 10 address bits A0 A9 will work properly with the VL 586 1 when addressed in the following I O ranges 2E8h 2EFh IOMAP1 Bit must 1...

Page 36: ...Bit must 1 See page 27 0200h 027Fh IOMAP2 Bit must 1 See page 27 1000h FFFFh Always enabled USING PC 104 MODULES All PC 104 modules decode 10 address bits A0 A9 and will work properly with the VL 586 1 when addressed in the following I O ranges 100h 16Fh IOMAP2 Bit must 0 See page 27 177h 1EFh IOMAP2 Bit must 0 See page 27 200h 27Fh IOMAP2 Bit must 0 See page 27 2E8h 2EFh COM4 Range IOMAP1 Bit mus...

Page 37: ...ated in real time under program control 0000h 00FFh On Board Devices 0100h 016Fh IOMAP2 0 PC 104 Bus 1 STD Bus IOEXP Signal Driven High 0177h 01EFh IOMAP2 0 PC 104 Bus 1 STD Bus IOEXP Signal Driven High 01F0h 01FFh Undefined 0200h 027Fh IOMAP2 0 PC 104 Bus 1 STD Bus IOEXP Signal Driven High 0280h 02E7h Undefined 02E8h 02EFh COM4 IOMAP1 0 PC 104 Bus 1 STD Bus IOEXP Signal Driven High 02F0h 02FFh Un...

Page 38: ...422 OPERATION For RS 422 operation jumper V1 should be jumpered as shown Note This configuration inserts a 100 Ohm line termination resistor in the circuit An equivalent resistor must exist at the opposite end of the cable to form a 50 Ohm balanced transmission line RS 485 OPERATION Removing V1 9 10 leaves the data circuit unterminated so that COM2 can be used as an intermediate station in an RS 4...

Page 39: ...d to J1 pin 6A Out RS 232 mode Frees J1 pin 6A for CTS2 COM2 Out V1 5 6 RS 232 422 485 Mode Selector In RS 422 485 mode Out RS 232 mode Out V1 7 8 RS 422 485 Differential Line Driver Control In RS 485 mode Enables software control of the differential line driver Out RS 422 mode Permanently enables the differential line driver Out V1 9 10 RS 422 485 Transmission Line Termination In Terminates data ...

Page 40: ...NFIGURATION Jumper blocks V19 and V18 are used to select the bus mastering mode Table 8 Multiprocessor Configuration Jumpers Jumper Block Description As Shipped V18 1 2 CPU response to SYSRESET In CPU resets whenever STD Bus SYSRESET P47 goes low Out CPU ignores activity on STD Bus SYSRESET P47 Out V18 3 4 Push button Reset Bus Interconnect In Connects STD Bus PBRESET P48 to CPU reset circuits Out...

Page 41: ... and respond to the STD Bus signals SYSRESET and PBRESET in different ways depending on the bus master mode Permanent Master The CPU is reset by pressing the on board push button and optionally by a low level on PBRESET arriving on the bus Permanent masters are responsible for driving the SYSRESET signal to reset temporary masters in the same card cage which are configured to react to SYSRESET To ...

Page 42: ...sources on the VL 586 1 Each jumper block is used to select one of two interrupt sources and route it to the interrupt controller Wire wrap techniques can be used to route interrupt sources to the CPU s IRQ inputs if the factory provided jumpers do not provide suitable connections Note Jumpers shown in as shipped configuration Figure 7 Interrupt Circuit Diagram ...

Page 43: ...RQ10 Out Disconnects CTC2 from IRQ10 Out V14 1 2 Interrupt Configuration IRQ11 INTRQ2 interconnect In Connects STD Bus INTRQ2 P50 to IRQ11 Out Disconnects STD Bus INTRQ2 from IRQ11 In V14 2 3 Interrupt Configuration IRQ11 Counter Timer 3 interconnect In Connects Counter Timer 3 Output to IRQ11 Out Disconnects CTC3 from IRQ11 Out V15 1 2 Interrupt Configuration IRQ12 INTRQ3 Interconnect In Connects...

Page 44: ...f multiple CPU s are used typically only one CPU will be jumpered to respond to NMI INTRQ INTRQ P44 General purpose or Interprocessor Communications Interrupt IPC INTRQ can also be jumpered to drive IRQ9 or IRQ3 INTRQ can also be used to carry the Interprocessor Communications Interrupt IPC between multiple CPU s by inserting jumper V17 1 2 Activity on INTRQ will drive IRQ5 INTRQ1 INTRQ1 P37 Gener...

Page 45: ... not available to the outside world IRQ1 09h Keyboard Hardwired to on board keyboard controller DOS BIOS expects keyboard interrupts on this input IRQ2 0Ah Slave Interrupt Controller Hardwired to secondary PIC Internal signal not available to the outside world IRQ3 0Bh COM2 COM2 DOS BIOS usually expects COM2 interrupts on this input Comes from the on board COM2 circuitry or from STD INTRQ Also con...

Page 46: ... IRQ9 71h Unassigned INTRQ From front plane interrupt connector STD INTRQ or PC 104 bus IRQ10 72h Unassigned INTRQ1 From Timer 2 STD INTRQ1 or PC 104 bus IRQ11 73h Unassigned INTRQ2 From Timer 3 STD INTRQ2 or PC 104 bus IRQ12 74h Unassigned INTRQ3 From Timer 4 STD INTRQ3 or PC 104 bus IRQ13 75h Math Coprocessor Hardwired Internal signal not available to the outside world IRQ14 76h Hard Disk Drive ...

Page 47: ...escription As Shipped V17 1 2 IPC Configuration IPC INTRQ interconnect In Connects IPC signal to STD Bus INTRQ P44 Out Disconnects IPC from INTRQ Out V17 2 3 IPC Configuration IPC INTRQ4 interconnect In Connects IPC signal to STD Bus INTRQ4 P05 Out Disconnects IPC from INTRQ4 Out NON MASKABLE INTERRUPT CONFIGURATION Jumper V18 5 6 is used to connect the STD Bus NMIRQ P46 signal to the CPU NMI inpu...

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Page 49: ...part on the card cage Caution Cards can be extremely sensitive to ESD and always require careful handling After removing the card from its protective wrapper or from the card cage place the card on a grounded static free surface component side up Use an anti static foam pad if available but not the card wrapper Do not slide the card over any surface The card should also be protected during shipmen...

Page 50: ...slot it is reserved for a bus arbiter or a power supply card STD 80 BUS INSTALLATION GUIDELINES An 8 bit STD 80 card cage like VersaLogic s VX Series can be used if cost savings are a prime consideration over performance however the use of 8 bit cages greater than six slots is not recommended due to the high performance bus drivers used on the VL 586 1 An 8 bit STD Bus card cage may be a good choi...

Page 51: ... describes the external interfaces available on the VL 586 1 CPU card CONNECTOR FUNCTIONS Table 14 Connector Functions Connector Function J1 High Density I O Connector J2 Front Plane Interrupt Connector J3 Floppy Drive Connector L1 Speaker Connector CONNECTOR LOCATIONS Figure 8 Connector Locations ...

Page 52: ...ta bit 5 18A 17 Select input 18B 8 Data bit 10 19A 5 Data bit 4 19B 9 Data bit 4 20A 18 Ground 20B 10 Data bit 11 21A 6 Data bit 5 21B 11 Data bit 3 22A 19 Ground 22B 12 Data bit 12 23A 7 Data bit 6 23B 13 Data bit 2 24A 20 Ground 24B 14 Data bit 13 25A 8 Data bit 7 25B 15 Data bit 1 26A 21 Ground 26B 16 Data bit 14 27A 9 Data bit 8 27B 17 Data bit 0 28A 22 Ground 28B 18 Data bit 15 29A 10 Acknowl...

Page 53: ...5 Ground Ground 6 DSR Data Set Ready In 7 RTS Request To Send Out 8 CTS Clear To Send In 9 RI Ring Indicator In Table 17 JA RS 422 485 Serial Port Connector Pinout DB 9 Pin Male RS 422 RS 485 JA Pin Signal Name Description Direction Signal Name Description Direction 1 N C N C 2 TD2 Transmit Data Positive Out TD2 Transmit Data Positive Out 3 N C N C 4 RD2 Receive Data Negative In TD2 RD2 Transmit R...

Page 54: ...Direction 1 STB Strobe Out 2 PD0 Data bit 1 In Out 3 PD1 Data bit 2 In Out 4 PD2 Data bit 3 In Out 5 PD3 Data bit 4 In Out 6 PD4 Data bit 5 In Out 7 PD5 Data bit 6 In Out 8 PD6 Data bit 7 In Out 9 PD7 Data bit 8 In Out 10 ACK Acknowledge In 11 PBSY Port busy In 12 PE Paper End In 13 SLCT Select In 14 AFX Auto feed Out 15 PERR Printer error In 16 INIT Reset Out 17 SLIN Select input Out 18 Ground Gr...

Page 55: ...C4 Counter Timer 4 Input This TTL input signal is used as the primary input control signal for counter timer 4 OCTC4 Counter Timer 4 Output This TTL output signal is the primary output control signal for counter timer 4 ICTC5 Counter Timer 5 Input This TTL input signal is used as the primary input control signal for counter timer 5 OCTC5 Counter Timer 5 Output This TTL output signal is the primary...

Page 56: ...OARD CONNECTOR A standard IBM PC keyboard can be attached to connector JD Table 20 Keyboard Connector Pinout 6 Pin Mini DIN PS 2 Style JD Pin Signal Name Function 1 KBDATA Keyboard Data 2 N C No Connection 3 GND Ground 4 5VCC 5V 5 KBCLK Keyboard Clock 6 N C No Connection ...

Page 57: ... 6 HDD9 Data bit 9 7 HDD5 Data bit 5 8 HDD10 Data bit a 9 HDD4 Data bit 4 10 HDD11 Data bit 11 11 HDD3 Data bit 3 12 HDD12 Data bit 12 13 HDD2 Data bit 2 14 HDD13 Data bit 13 15 HDD1 Data bit 1 16 HDD14 Data bit 14 17 HDD0 Data bit 0 18 HDD15 Data bit 15 19 GND Ground 20 N C No connection 21 N C No connection 22 GND Ground 23 HDIOW I O write 24 GND Ground 25 HDIOR I O read 26 GND Ground 27 HDIORDY...

Page 58: ...e interrupt request input If jumper V12 2 3 is inserted a low level or high to low transition applied to the FP0 pin will request an interrupt via IRQ9 In DOS configuration this will cause an INT 71h resulting in a dispatch through the interrupt vector at 000 01C4h FP1 Front Plane 6 Interrupt This TTL input signal is used as a general purpose interrupt request input If jumper V16 1 2 is inserted a...

Page 59: ...ace Connector Pinout J3 Pin Signal Name Function J3 Pin Signal Name Function 1 Ground Ground 18 DIR Direction Select 2 R LC Load Head 19 Ground Ground 3 Ground Ground 20 STEP Motor Step 4 NC No Connection 21 Ground Ground 5 Ground Ground 22 WDAT Write Data Strobe 6 NC No Connection 23 Ground Ground 7 Ground Ground 24 WGAT Write Enable 8 INDX Beginning Of Track 25 Ground Ground 9 Ground Ground 26 T...

Page 60: ...tallation VL 586 1 Reference Manual L1 SPEAKER CONNECTOR Connector L1 is provided for connecting an 8Ω speaker to the card Table 24 Speaker Connector Pinout L1 Pin Signal Name Function 1 Timer 2 Out Speaker drive 2 Ground Ground ...

Page 61: ... Undocumented PC listed in Other References on page vi Register Summary The tables in this section list all programmable registers on the VL 586 1 CPU card They are organized in the following groups Table 25 Programmable Registers Registers Page DMA 1 Controller 52 DMA 2 Controller 53 DMA Page 53 COM1 Serial Port 54 COM2 Serial Port 54 LPT1 Parallel Port 55 82C735 Configuration Interrupt Controlle...

Page 62: ...nt Word Count DMA2ADRA R W 0004h DMA Channel 2 Current Address DMA2CNTA R W 0005h DMA Channel 2 Current Word Count DMA3ADRA R W 0006h DMA Channel 3 Current Address DMA3CNTA R W 0007h DMA Channel 3 Current Word Count DMACSA R W 0008h DMA Command Status Register DMARQA R W 0009h DMA Request Register DMAMASKA R W 000Ah DMA Single Bit Mask Register DMAMODEA R W 000Bh DMA Mode Register DMACBPA R W 000C...

Page 63: ... Status Register DMARQB R W 00D2h DMA Request Register DMAMASKB R W 00D4h DMA Single Bit Mask Register DMAMODEB R W 00D6h DMA Mode Register DMACBPB R W 00D8h DMA Clear Byte Pointer DMAMCB R W 00DAh DMA Master Clear DMACMB R W 00DCh DMA Clear Mask Register DMAWAMB R W 00DEh DMA Write All Mask Register Bits DMAWAXB R W 00DFh DMA Write All Mask Register Bits X DIRECT MEMORY ACCESS PAGE REGISTERS Tabl...

Page 64: ...Modem Control Register A LSRA R 03FDh Line Status Register A MSRA R 03FEh Modem Status Register A SCRA R W 03FFh Scratchpad Register A COM2 SERIAL PORT Table 30 COM2 Serial Port Registers Mnemonic R W Address Name RBRB R 02F8h Receiver Buffer Register B THRB W 02F8h Transmit Holding Register B DLLB R W 02F8h Divisor Latch LSB B IERB R W 02F9h Interrupt Enable Register B DLMB R W 02F9h Divisor Latc...

Page 65: ...ble 31 LPT1 Parallel Port Registers Mnemonic R W Address Name LPRD R 0278h Line Printer Read Data Register LPWD W 0278h Line Printer Write Data Register LPS R 0279h Line Printer Status Register LPRC R 027Ah Line Printer Read Control Register LPWC W 027Ah Line Printer Write Control Register ...

Page 66: ... W 03F7h Data Rate Register FDCFDR R 03F7h Fixed Disk Register IDE HARD DISK DRIVE CONTROLLER Table 33 IDE Hard Disk Drive Controller Registers Mnemonic R W Address Name IDEDR R W 01F0h Data Register IDEER R 01F1h Error Register IDEWP W 01F1h Write Precompensation Register IDESC R W 01F2h Sector Count Register IDESN R W 01F3h Sector Number Register IDECNL R W 01F4h Cylinder Number Register Low IDE...

Page 67: ...0020h In Service Register IRRA R 0020h Interrupt Request Register IPWA R 0020h Interrupt Poll Word IMRA R 0021h Interrupt Mask Register INTERRUPT CONTROLLER SLAVE Table 35 Slave Interrupt Controller Registers Mnemonic R W Address Name ICW1B W 00A0h Initialization Command Word 1 ICW2B W 00A1h Initialization Command Word 2 ICW3B W 00A1h Initialization Command Word 3 ICW4B W 00A1h Initialization Comm...

Page 68: ...Read TCW0 W 0043h Timer Control Word Table 37 Channels 3 to 5 Mnemonic R W Address Name T3CNT R W 0044h Timer 3 Count Load Read T4CNT R W 0045h Timer 4 Count Load Read T5CNT R W 0046h Timer 5 Count Load Read TCW3 W 0047h Timer Control Word MISCELLANEOUS Table 38 Miscellaneous PC AT Style Registers Mnemonic R W Address Name CSP R W 0061h Control Status Port RTCIDX W 0070h Real Time Clock Index and ...

Page 69: ...block V17 configures the TIPC signal to be carried on the STD Bus signal INTRQ P44 As an alternative TIPC can be carried on the STD Bus signal INTRQ4 P05 An active low signal on this circuit generated locally by writing a 0 to this bit or received from the STD Bus requests an interrupt on IRQ5 In DOS configuration this causes an INT 0Dh resulting in a dispatch through the interrupt vector at 0000 ...

Page 70: ...card to reset the CPU if proper software execution fails or a hardware malfunction occurs The watchdog timer is enabled disabled by writing to bit D0 of SCR If the watchdog timer is enabled software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire 250 ms Writing a 5Ah to WDHOLD resets the watchdog time out period preventing the CPU from being reset for ...

Page 71: ...to CFFFFh PC 104 Bus MMAP2 1 C8000h to CFFFFh STD Bus D2 MMAP1 Memory Map Select 1 Selects PC 104 or STD Bus memory access MMAP1 0 D0000h to D7FFFh PC 104 Bus MMAP1 1 D0000h to D7FFFh STD Bus D1 IOMAP2 I O Map Select 2 Selects PC 104 or STD Bus I O access IOMAP2 0 0100h to 01EFh 0200h to 027Fh IOMAP2 1 0100h to 01EFh 0200h to 027Fh Note See I O map on page 27 for further information D0 IOMAP1 I O ...

Page 72: ...c Description D7 FPAGE Flash Paging Enable Enables a 64K page frame from E0000h to EFFFFh Used to gain access to the on board FLASH or BBSRAM FPAGE 0 Page Frame Disabled FPAGE 1 Page Frame Enabled D6 Reserved This bit has no function Always reads as 0 D5 D0 RPG5 RPG0 Page Select Selects which 64K block is mapped into the page frame RPG5 RPG4 RPG3 RPG2 RPG1 RPG0 Memory Range 0 0 0 X X X 8 Pages BBS...

Page 73: ...VL 586 1 Reference Manual Appendix A Schematic 63 Appendix A Schematic A ...

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Page 82: ...Control Registers 56 External Connector JF 42 47 Interface 2 I O Control Registers I O and Memory Map IOMMAP 61 I O Map 25 27 IOEXP 25 Register Summary 51 Installation Card Insertion and Extraction 40 Card Orientation 40 Overview 39 Interrupts Block Diagram 32 Configuration 32 Controllers 3 57 Destinations 32 External Connector J2 48 General Purpose 34 Interprocessor Communications 34 37 59 Keyboa...

Page 83: ...35 PC 104 Bus Description 2 Interrupts 35 Push button Reset 31 Real Time Clock Description 3 Interrupts 35 Reset 31 RS 232 422 485 See Serial Ports Serial Ports 2 Control Registers 54 External Connectors JA JE 42 43 Interrupts 35 RS 232 422 485 28 43 Setup See Memory Speaker External Connector L1 50 Special Control Register 59 Specifications 4 Static RAM See Memory STD STD32 Bus Description 2 Tech...

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